Design And Realization On The Digital Data Link Of TD-LTE Terminal Test Set

The thesis presents the work of TD-LTE Terminal Test Set. The test set can be made up of RF transceiver, baseband signal processor, clock generator and center processor. The thesis is mainly about the design and realization on the digital data link in FPGA both in the RF and baseband unit. In the baseband unit, the author implements OBASI between DSP and FPGA and Aurora between RFU and BBU.Because of the high speed of the data, the transferring is very important. In the RF unit, the author implements data filter and combination, DDC/DUC module, variable rate data processing module, analog filter compensation module, compensation of IQ DC offset and amplitude module, power compensation module. The variable rate data processing module provides high performanced interface to BBU. Besides, the design and implementation of this module reduce the resources cost in FPGA. The algorithms compensate for the performance of RFU. The data link in test set is basal but pivotal, which is an important part of TD-LTE Terminal Test Set.The thesis is involved in all the software and hardware R&D flow in design and realization on the digital data link of TD-LTE Terminal Test Set, including requirement analysis, general design, particular design, coding, verification and debugging. The main contents of this paper are organized as follows:1. The origin of the task and the meaning of the research are introduced. And then the author introduces the principle of FPGA and Xilinx's latest features of V5 series FPGA chips and briefly introduces GTP and DSP48e, which are the primitives in V5 series FPGA. 2. The whole design scheme of the digital data link is introduced. And the performance parameters and the key questions are especially emphasized.3. According to the general design, the author focuses on the design and realization the digital data link, which includes transmitter, receiver and so on.The thesis focuses on the realization of variable rate data processing module based on the resources cost in FPGA4. The author simulates the key modules of the system and then analyzes the simulation results. In the end, the author tests the key modules to verify effectiveness and reliability.5. The experience in the progress of project development is summarized at the end part of this thesis. The thesis has an outlook of TD-LTE test set on future.