Research And Design Of Network Encryption Card

With the fast development of Internet and the advancement of global information process, the issues of network security are also aggravating increasingly. The cryptographic technology is an important way to ensure information security, and it is the kernel of information security. In all kinds of encryption algorithms, the block cipher has many advantages, such as high speed of encryption and decryption, easy to standardize and convenient to implement by both software and hardware, so it is always the crucial standard to implement data encryption, digital signature and key management. AES algorithm is a respective one among block algorithms.This paper introduces the implementation principle and encryption process of AES algorithm in detail, and does the implementation of AES algorithm by using VHDL due to the advantages of FPGA, such as flexible design, high reliability and good scalability. What's more, this paper makes some optimization such as merger of Sub Bytes and Shift Rows, Mix Columns/Inverse Mix Columns optimization, which reduce hardware area to a large extent, increases the hardware speed of encryption/decryption, and achieve a tradeoff between throughput with area and speed.The optimized implementation of AES algorithm based on FPGA builds a good platform for the design of network encryption card. On the basis of mastering network transmission protocol and data transmission principle, the paper designs the overall architecture of the card from the beginning and then between PCI and network card, FPGA encryption chip is added, which contains PCI interface and data encryption/decryption module that the optimized implementation before is applied.