Design And Research Of A High Gray-scale LED Screen Control System Based On FPGA

In such a society where information technology is developing rapidly, the release and transmission of information is becoming more and more important, how to transmit information instantaneously, realistically and vividly has become a growing topic of concern. Information dissemination in the hospital, financial sites, transportation sites, stadiums, shopping malls and other public places has been widely used, so a variety of information display technology has emerged. LED display technology which has a long life, high brightness, easy maintenance, advanced technology and many other advantages is becoming the most rapid development and the most widely used display technology in recent years.This paper presents a high gray-scale LED screen control system based on FPGA, and FPGA devices have many advantages such as high integration, high speed and online programming, and they both can meet requirements of the video display system for data processing speed and can increase flexibility of design, and the system can be upgraded through online programming.This paper systematically introduces the basis concepts of FPGA and the background of LED display technology, and shows the advantages of FPGA circuit design and the development prospects of LED display technology. The main object of study in this paper is the high gray-level LED display control system, and the paper proposes a system implementation based on FPGA by the means of hardware and software combination, and the entire system is divided into two parts: DVI decoder circuit, FPGA data processing and control module. This paper gives a transmission scheme based on single-link TMDS through the research of grayscale data transmission speed while designing DVI decoding circuit. After determining the transmission scheme this paper describes the hardware design of DVI decoding module in detail, and then describes the external circuit design, grounding and power design solution of DVI decoder chip SiI1161 specifically. Finally the paper describes the design of hot swap cell based on DDC2B protocol. While designing FPGA data processing and control module the top-level module will be divided into four parts in accordance with top-down design solution. The four parts are anti-γcorrection module, data separation and restructuring module, grayscale scan control module and SRAM reading and writing control module. And four modules are described separately in this paper. Because FPGA chip is volatile after power-down, the chip must be re-configured after each power. The paper uses a combination of active + JTAG solution to configure the FPGA chip, and such a configuration scheme can meet the needs of commissioning and setting phase. The paper analyses the drawbacks of the hardware implementation scheme in the anti-γcorrection module. The system will adopt the means of look-up table mapping to achieve anti-γcorrection and the system will achieve 1024 levels of gray scale. The software design scheme is open and we can update anti-γcorrection table with the change of the external environment. And the software scheme has strong environmental adaptability. Because the gray scan of the LED display is based on weights, I must separate and recombine the grayscale data after anti-γcorrection. I use the implementation of horizontal writing and vertical reading in separation and recombination module. The paper analyses blanking level control mode based on time of different lengths. Because the scanning frequency of the system is only 60Hz, the display will appear blinking phenomenon if adopting the scan method above. So the system proposes a scan control scheme of breaking up the gray pulse through improving blanking level control mode based on time of different lengths. The grayscale implementation scheme can not only reduce gray scanning frequency but also meet the system requirements of high gray level. The system uses an alternating reading and writing double memory scheme in order to achieve buffering and reading gray data with no time interval. SRAM reading and writing control module can be divided into three sub-modules. The sub-modules are reading address generation module, writing address generation module and writing and reading control module. Reading address generation module generates address in accordance with the color and weight, and writing address generation module generates address in accordance with the color. Eventually the system outputs valid address, valid data and effective reading and writing signals of the memory under the control of reading and writing control module.Finally Verilog hardware description language is applied to describe the programming of each sub-module and EDA development tool Modelsim is used to simulate sub-modules to show the correctness of the scheme. At last QuartusII is used to design and verify the top module in this paper.