Research And FPGA Design Of Deinterlacing System Based On Motion Compensation

With the high-speed development of high-end television, the research and application of digital television technique, the flaws caused by interlaced scan in traditional analog television, such as color-crawling, flicker and fast-moved object's boundary blur and zigzag, are more and more obvious. However, because of the economic development, analog television will still take its place in the TV market during a long period. Therefore the conversion of interlaced scan to progressing scan, which is deinterlacing, is an important part of current television production, such as digital video post-processing.As the real-time require of television signal processing, most deinterlacing system adopt non-motion compensation-base algorithms, which are small calculation account and easy realized. Nowadays with the development of semiconductor, the improvement of VLSI and the application of ASIC technique, people can apply the motion compensation-base algorithms to consuming television productions.This paper applies the motion compensation-based algorithm to deinterlacing system and deeply researches the FPGA design of the system. There're three key modules in the system, which are motion estimation module, motion compensation module and buffer module. The motion estimation module is the most important part of the deinterlacing system, which is designed as bi-directional motion estimation. It applies diamond search algorithm. Compared with full search algorithm, it has less calculation account and more complex control. There are two parts in the module, which are calculation and control part. The calculation part is SAD calculation module. It applies adder-tree and pipeline technology. And based on the characteristic of the third search step in diamond search algorithm, the control part makes special designs for comparison module , SAD buffer, etc. to improve the calculation efficiency of motion estimation module. As to motion compensation module, bi-directional compensation algorithm is used. The precision is half pixel. Based on the position of half pixel, there are four states in motion compensation calculation. After analyzed the characteristic of four states calculation, the adder's diplex structure is designed, which can save large resources. And for the request of video data processing, four inner buffers are designed, which are structured by dual body. They are realized by embedded array block in FPGA. Also their structures, writing and reading timing and column control are designed based on the calculation characteristics of motion estimation and motion compensation module, which can effectively improve the data's access efficiency. The three key modules are all presented as RTL level design and module functional simulation. The deinterlacing system's FPGA design is in the last chapter.