The Design Of Head Rice Sorting Meter

In our country, the separation of rice still depends on manual work, which is inefficient. In order to realize machine sorting, a head rice sorting meter is designed based on the requirement of head rice yield.The control system of this apparatus is implemented by ARM9. It develops a touch screen as human computer interaction(HCI) to co-work with supply system, photoelectric separation system and weighing system. The control system controls supply system to provide rice, then photoelectric separation system sorts the falling rice, and eventually head rice yield is calculated.The major part of this paper is the development of photoelectric separation system. FPGA chip XC3S500 and CPLD chip XC9856 are used as control chip to separately drive an imagedigitizer TLR9830 and a CCD image sensor TCD3082, then offer a sorting signal. FPGA is connected to ARM main controller through serial communication module.The hardware circuit of the system consists of CCD image acquisition circuit drived by CPLD, A/D sampling circuit drived by FPGA, serial communication module and the design of airgun separation circuit. The software designment consists of CCD driving time sequence, A/D sampling driving progam, image data processing including algorithm recognition and saving, and data serial communication design.Under ISE8.2 compiling environment, with the help of XST simulatioin and Synplify Pro synthesis software, we use Verilog HDL to implement a top-down module progamming. ChipScope is used to debug the system on line. Finally the debugging and performance testing of the whole system proves that the system runs stable and HCI is convenient. The accuracy of head rice yield can be realized well.