Research Of Synthesis Method For IP-Reused-based Reconfigurable Architectures

The development of next-generation computer-aided design tools and field reconfigurable architectures require high-level data-flow synthesis with enhanced algorithms. In addition to, no validation is done on the high-level data-flow synthesis as existing synthesis tools are used on reconfigurable architectures, and designer have a lot of bother choosing the side relation set.Polynomial representation has been proven as an effective technique for representing both high-level specification and system-level description of an implementation. Popov form shows the property of simplicity in polynomial theory. During researching synthesis method to IP reuse for the reconfigurable architectures, this paper brings to bear polynomial theory to improve the algorithms. It can be transformed into the representation of polynomial matrix by the rules. This paper decomposes the one into shifted Popov polynomial matrix and minimal multiplier in order to make the best of the reuse technology and implement high-level synthesis for reconfigurable logic.In this paper, the approach is showed to how polynomial theory can be used to construct the decomposition algorithm. It is gained to minimal multiplier and shifted Popov polynomial matrix by the algorithm in order to synthesize system and present simple verify approach for reconfigurable architectures. On second thoughts, this paper makes use of the parallelism of polynomial matrix multiplication to speed up optimization. It is obtained to a minimal state-space realization of the system. In this paper, it is showed to some examples and experiment results, which explain that the algorithm is validated on the high-level data-flow synthesis for reconfigurable architecture. Compare with existing tools, it has some advantage because it does not require finding the side relate set, and is extensible for future research.The pipeline technologies are utilized to solve reconfigurable architectures with constraints. It is wished to map loops onto a reconfigurable architecture, subject to various performance constraints such as throughput, power, energy or area.Basing on pipeline technology, scheduling algorithms allow to trade-off the degree of acceleration with power, energy and/or area constraints.