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Carrier Synchronize's Design And Implement Of WLAN

Posted on:2006-07-04Degree:MasterType:Thesis
Country:ChinaCandidate:Z X WangFull Text:PDF
GTID:2168360155460848Subject:Control theory and control engineering
Abstract/Summary:PDF Full Text Request
With the development of society, the technology of WLAN (Wireless Local Area Networks)has become the most important part of our life. The Terminal device is one of the most important parts of WLAN system. The Wireless Network interface of terminal device is the key point of linking between terminal device and network. The design and implement of physical layer of WLAN is the kernel and difficult in the development of WLAN system. The physical layer support security, compatibility, stability, resist interfere. Carrier synchronize system use DPLL (Digital Phase Lock Loop) to synchronize the signal. It compensate the frequency error and phase error caused in channel. It is the good method of improvement of transport veracity and lower fault code rate. With the influence of channel to signal, we get the mathematic module of receive signal and summarize the signal parameter that need to be deal with by estimate method. Using Maximum-likelihood estimation, we choose the decision feed back carrier estimate method based sent list known. Because the need of carrier synchronization, after estimation of carrier synchronization's phase error, return the error to signal, this is a feedback cycle loop (decide feed back loop), a special DPLL. After receive the global scheme, based the decode recode method of WLAN, transportation method of WLAN and the character of sequence and phase of carrier phase error, we find the design way of this special DPLL's several departments. Using the theory of automatic control, We do the analyze and emulator of the character of track and capture of this PLL. The result of emulator realize that this design satisfy the need of the WLAN receiver system. We also do the analyzes and emulator of the stability of sequence and phase error capture. Because WLAN terminal device must be portable, this system is implemented by using thinking in SoC. The article analyzes the delay, source using and bitwise restrict of hardware design. Though FPGA verify, this system satisfy the need of WLAN system and is very strong in stability and practicability.
Keywords/Search Tags:WLAN, Digital carrier synchronization, PLL, DPLL, SoC
PDF Full Text Request
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