Investigation On The Channel Estimation Scheme For The MIMO System

The global wireless communications has entered a high-rate broadband multimedia and real-time data application age. The Multiple Input Multiple Output (MIMO) technology can dramatically increase the channel capacity. As a result, the whole communications field generally believes that the MIMO will become one of the key technologies of the next generation mobile communications system. There is more and more domestic and foreign scholars' attention focused on it. This thesis introduces the channel estimation in the MIMO system, and implements the algorithm of the channel estimation for the MIMO system on the FPGA.First of all, on introducing the concepts of the MIMO technology and researching actuality, the thesis describes the structure of the MIMO demo system. The physical layer is the core of this system and the channel estimation is one of the receiver modules in this layer.Secondly, the components of the physical layer of MIMO system are introduced and some key technology of MIMO is emphasized at the same time, such as Space-Time-Block-Code, Time-Domain-Diversity-Combining and Cyclic Prefix, etc. The channel estimation assisted by training sequences is the major subject of this thesis, so more attention was paid on channel estimation in this part and the simulation performance was also given.The next in order, the algorithm transplantation procedure from the float-point to fixed-point is discussed. After declaring the necessity and rule of fixed-point procedure, the fixed-point configurations of every module in physical layer are given. These entire configurations directly lead the FPGA realization. The results of the fixed-point simulation of MIMO system show that there is about 1dB loss of the BER performance comparing to the float-point simulation.At last, some important considerations in the FPGA realization of channel estimation and some other modules are explained in detail, which is based on the fixed-point simulation. In the end, all these FPGA realization will be downloaded to the digital baseband signal processing board.