The Research And Implementation Of Low Bit Rate Video Codec Based On DSP

With the fast development of modern information age, the researches and applications of data communication and signal processing technology catch great attentions from researchers all over the world. At the same time, the design of the high performance video-telephony application over PSTN has become an active research area. In recent years, the development of DSP technology has pushed the research progress of the video-telephony system, and widely put the theory achievements of digital signal processing field into practical systems. In this paper, we present a hardware and software implementation approach of real-time H.263 codec based on TI's TMS320C80, a digital signal multiprocessor with a highly parallel instruction set. The algorithm, bit stream syntax and the procedure of coding and decoding of H.263 are studied first in this paper. Then it introduces the structural and the functional features of TMS320C80 in detail. After that, with all of the prelude above, the implementation scheme of H.263 codec with TMS320C80 as the core processor is put forward. This approach also employs those chips such as VP520, BT851, BT819 to process the video signals including convert the signal format. The design techniques of each function module of this system and problems in realization are analyzed in detail. Meanwhile, methods of determining the interface timing are discussed. Afterwards, under the consideration of tradeoffs between processing speed and system performance, we mainly address the key techniques of the video codec. Optimized solutions are provided to tackle those time-consuming tasks and the system level as well as some specified module flowcharts of software are presented. Also, in the scope of the implementation of each module, the parallel processing techniques, such as ping-pang mode and pipeline mode, are addressed thoroughly to show how they can help to make the software more efficient.This paper also introduces some specific methods and procedures of debugging the whole system. At last, some of those difficulties that we have met and corresponding solutions are addressed. The developing procedures of hardware platform and the implementing of system software are covered in this paper. We also make experiments of the codec on the target board. The analysis of the experiment results indicates that the implementation scheme of this system is highly qualified to accomplish the task of real-time H.263 encoding and decoding.