Research On PCI IP And PCI Related ASIC Design Techniques

PCI (Peripheral Component Interconnect) bus, which has been the first chosen in recent years for PC local bus because of its high performance, is an excellent bus for multimedia. It is a challenge for R&D department of VLSI to design a PCI bus interface.This dissertation is supported by the following projects: the project of "The Development and Commercial Usage of Embedded 32-bit MCU" from MII and the project of "The Development of Security Chip Based on PCI IP" from the Institute of VLSI Design, Hefei University of Technology.The main work and achievements are as follows:1. PCI Slave bus protocols on the inner of the PCI interface is established The inner protocol includes the consideration of three level data buffer. The design of three level data buffer will increase the data transfer speed of PCI and decrease the using time of PCI.2. The methodology of designing the PCI bus interface IP core is discussed. A design method of PCI Slave IP which based on multi-state machine structure is proposed. The measurement for transaction safety and data buffering are valid for other large interface circuit design.3. The automatic synthesis of interface between PCI inner protocol and PVCI (Peripheral Virtual Component Interface) is discussed. A design method of interfacing which based on state machine structure is proposed.4. On the base of investigating the properties of PCI address/data bus and the sequence of read, a re-use model of PCI address/data bus is proposed. The model is not only working perfectly, but also reducing the pin resource, die size and costs.5. The methodology of interfacing with EPROM/EEPROM is discussed. An interfacing model with parameter timing is proposed.The contents of the dissertation has been verified by FPGA ( Field Programmable Gate Arrays) . The model for re-use PCI address/data bus and the chip for PCI bus security have been verified by ASIC.