Study On Built-In Self-Test Methodology For Fault Diagnosis Of Mixed-Signal Circuits

Progress in very deep submicron semiconductor technology enables the integration of a highly complex system on one single chip, it is so called System-on-Chip (SOC). With the increasingly stringent requirements of market such as mobile communications and consumer electronics, SOC chip has turned from digital SOC to mixed-signal SOC that includes sophisticated digital signal processor, memory, real time operation system, high-performance analog and mixed-signal function, etc. As integration complexity increases, there exist many new difficulties in testing embedded analog cores in mixed-signal SOC. The application of Built-in-self-test (BIST) can reduce the SOC test and verification time, and improve the fault coverage. Therefore, the BIST technique is an important approach to efficiently test analog blocks of mixed-signal SOC. This dissertation focuses on test methodology of mixed-signal integrated circuits. Author's main work concentrates on four aspects as follows: 1.On testability analysis for analog integrated circuits.(1) Testability measure of analog integrated circuits: Not only does analog testability measure provide a quantitative criteria to compare different testable methodologies, but also is used to select an optimum set of test points and determine canonical ambiguity groups in the circuits. In this dissertation, analog testability measure is defined as the column-rank of sensitivity matrix of fault diagnosis equations, and a formula applied to multiple inputs and outputs system is deduced.(2) Simplification of testability measure calculation: In order to fully automate the testability measure computation, decrease the time complexity and avoid the truncation errors introduced by numerical method, the relations between the determinant decision diagram (DDD) and the partial derivatives of the product-terms coefficients in the numerators and denominators of transfer functions with respect to faulty component parameters are constructed. (3) Improvement of testability: For the purpose of reducing test cost and obtaining higher fault coverage, several Design-for-Testability (DFT) methodologies of the circuit are concerned.2. On generating on-chip analog stimulus signal. To generate high-precision analog signal whose parameters, e.g. frequency, amplitude, phase can arbitrarily be set and decrease area overhead as possible, the properties of lossless discrete integrator resonator and high order sigma-delta modulator are studied. One method for realization of high order sigma-delta modulator based on a ladder of integrators is proposed, and DDD-based symbolic analysis is used to quantize the coefficients of the integrator-ladder structure. This structure can realize a closer approximation to a pole-zero distribution of original noise transfer function (NTF) than integrator-cascade because the NTF of integrator-ladder is less sensitive to the large coefficient variations induced by quantization. The method to generate on-chip stimuli consisting of multiple frequencies is also depicted.3. On DFT test methodology of the analog circuit fault. With the development of microelectronics technology, the chip integration scales increases continuously, resulting in decrease of the testability. First, ambiguity groups in the low testability circuits are discussed. Then, an approach to identify canonical ambiguity groups is presented, which need only one QR factorization of the testability matrix and doesn't require combinational searches. A structural BIST scheme applicable to mixed-signal integrated circuitry is investigated based on DFT of the circuits under test. Corresponding to this BIST scheme,two multiple fault diagnosis algorithms for low testability circuits and resistance networks are presented. The former demands two single frequency sinusoidal signals, the latter deals with the stimulus deviation caused by the component parameter tolerance.4. On constraint analysis for mixed-signal integrated circuitry. Additional circuit introduced by the DFT and BIST schemes increases the hardware overhead...