Analog IP Design And SOC Integration

With the development of semiconductor process technology a system on a PCB(Printed Circuit Board)which is composed of several ICs can be integrated into a chip. SOC (System On Chip) can improve the system performance greatly and solve various problems of a PCB system such as noise, speed limit caused by wire delay etc. It makes great sense for the development of information technology. However, as time-to-market pressures and chip complexity grow, current design tools and methodologies are inadequate for developing million-gate SOCs from scratch. Reuse of pre-designed and pre-verified circuit modules, known as IP(lntellectual Property), is the most promising method to bridge the gap between large gate number and designer productivity.After the discussion of SOC design methodology and technique an IP based SOC design is given in the dissertation.LINE is designed for the telephone with short message service function. A 32-bit imbedded microprocessor C*Core (coming from M Core in Motorola) is used as the brain of the system, some additional IPs such as RAM. interrupt controller. Serial Communication Interface, Serial Peripheral Interface are also integrated on the chip. The partition of software/hardware and the architecture design of hardware are completed in the system level design of LINE. The main goal of this dissertation is to present a design of the analog IP. called LVDRcset and the SOC integration of LINE. LVDReset is designed to detect supply voltage in order to protect the chip. After the schematic is verified by Spice simulation, the custom layout and physical verification are made. SOC integration is based on the pre-designed IPs. It is implemented by synthesis and auto place and route. In this process, however, hard IPs must provide enough and accurate information and models in addition to their design data.The design is implemented based on TSMC 0.25m technology with 4 metal. LINE has been taped out through the TSMC MPW (Multi-Project Wafer) project, and passed the final test.