MPEG-4 Standard Based Motion Estimation Hardware Accelerator Design Research

Recent years have witnessed the rapid growth of multimedia technology. A large amount of information of audio and video data is widely used, which causes a severe challenge to coding technology and standard. For this reason, the International Organization for Standardization (ISO) launched a number of coding standards, including the most promising MPEG-4 standard.From MPEG-1 to MPEG-4, even very popular H.264 standard utilize a lot of techniques to reduce the temporal and spatial redundancy, including motion estimation and motion compensation, discrete cosine transform, quantization, Huffman coding and so on. Among them, block matching based motion estimation and motion compensation is one of the most important components. Accurate and efficient motion estimation algorithm can greatly reduce spatial redundancy and bring high compression ratio. However, the computation of motion estimation is enormous. Therefore, it is useful to design a hard accelerator module to replace the software component, which can improve power consumption and performance of the multimedia chip.The thesis firstly makes a deep study of the basic principle of video coding and the syntax of MPEG-4 protocol, especially the motion estimation and motion compensation algorithms used in the standard. Then, the thesis analyzes various motion estimation and motion compensation algorithms and proposes a new algorithm based on hardware design requirements. After that, the thesis designs motion estimation accelerator structure which mainly includes accelerator interface, the internal registers and instruction set. Finally, the author writes the hardware accelerator simulation model in C programming language and rewrites the motion estimation and motion compensation code in open source codec XVID, which constructs a simulation platform. Based on this platform, the thesis designs the test cases and performs the simulation tests using the standard test sequences.Simulation results demonstrate that this hardware accelerator supports MPEG-4 standard, which can encode CIF and QCIF format frames. Meanwhile, it reduces block motion vectors'search computation by about 50 percent, but it does not lose the image quality and coding bits much. The method proposed in this thesis is suitable to be applied in low-end codec chips. The work in this thesis gives a constructive reference for the related work of domestic multimedia IC design companies.