The Study And Realization Of Image Procession And Compression Based On FPGA

With the background of "the dramatic inspect equipment of vehicle wheels" and the aim of improving the performance of the equipment, this paper studies about the realization of image collection and control, image processing algorithm, and JPEG basic system on the chip Cyclone from the Altera company's FPGA. With the hardware platform of the Redlogic's RVDK, it completes the design and the simulative confirmation of the soft core with the hardware descriptive language Verilog in the environment of the exploited tool QUARTUS2 6.0 and MODELSIM_SE6.1B.The function of the image collection part is to convert the analog data from the analog camera into the digital data, and then to pick up the useful data from the data flow, and finally to incorporate the odd and even field into a frame and save it to a memory after the appropriate cut. The function produced by the digital data flow is completed by SAA7113 chip, however, FPGA chip initializes and controls the SAA7113 chip, and manipulates the digital data as well.Taking account of some factors such as real time character complexity of algorithm, the image processing algorithm part chose three algorithms to realize, they were histogram equalization, median filter and edge inspection.According to the order coding mode of the JPEG basic system, the compressed code part realized DCT transform, quantized, Zig—Zag scan, DPCM encoding of direct current coefficient, RLC encoding of alternating current coefficient, Huffman encoding. Finally, an actual image data was used to validate the whole system.