Research On CAN-bus Controller Based On FPGA And Its Testing System

CAN-bus is a serial data transfer bus developed by Bosch Group in Germany in 1980'in order to solve the problem of data traffic in the instruments of automobiles. CAN-bus is a system with multiple terminals. The communication medium can be twisted-pair, coaxial-cable or fiber, and the speed of communication can reach up to 1Mbps. CAN-bus is made up of many nods, and every nod includes mcu, controller, transceiver. The controller of CAN-bus integrates the functions of both the physical layer and the transfer layer from the CAN specification. It can accomplish the multiple data processing tasks, including inserting/deleting the 0 bit, coding data modules, CRC, differentiating PRI, etc. A strongpoint of the CAN specification is it abolished the method of coding by address and used data modules instead. The merit is making the number of nodes grow as many as possible without a limitation. The ID of data module is made up of 11 bits (according to CAN specification 2.0A) or 29 (according to CAN specification 2.0B) bits binary system. So it can define 211 or 229 different data modules. This way of coding by data module also can enable different nodes to receive the same data simultaneously. It is very useful in the system of distributing control. There are at most 8 bytes in each data segment to satisfy the commonly requests from control commands, working states and testing data in industry fields. At the same time, 8 bytes do not have to cost too much time to occupy the bus. Hence, it enables the communication to be real-time. CAN specification also uses CRC and offers the function of error handling to ensure the reliability of communication. Because of these excellent characteristics and idiographic design, CAN-bus is adapted to use in the interlinkage of industry-process-control equipments. Therefore, CAN-bus is regard as the most important bus in the industry fields.In the first chapter of my thesis, I introduced the origin, the development, the characteristics and the relevant chips of CAN-bus. After that, I introduced the CAN specification as well. In the CAN-bus there are four different frames: (a) Data Frame. It carries data from the senders to the receivers. (b) Remote Frame. It is a transmitter sent by a bus unit to request the transmission of the Data Frame with the same ID. (c) Error Frame. It is transmitted by any unit in case of detecting a bus error. (d) Overload Frame. It is used to offer an extra delay between the preceding and the succeeding Data Frames or Remote Frames. Every frame is made up of different fields, and every field has its own function in the specification.In the second chapter of my thesis, I introduced a design of CAN-bus interface, inorder to provide a test entironment for our own design. Using SCM AT89S52 as MCU, the controller and driver are SJA1000 and PCA82C250 made by PHILIPS. In this chapter, I explained the designs of hardware and software. There are three parts in the software design containing initialization program, transmission data program, and receiving data program.In the third chapter of my thesis, I designed a FPGA board which could accomplish the functions as a controller of CAN-bus. The board supplies all ports in order to provide advantages for the future work. In my paper, the core chip of the board is EP1C6Q240C8 made by Altera. As for the power module, I used the chip named uA7805. The minimum input voltage is 7V, the maximum is 25V, and the output voltage is steady 5V. In addition, I used the AD chip AS1117 to obtain voltage of 1.5V and 3.3V in order to support the FPGA chip. The reset chip is an IMP811 made by Maxim in the U.S., and its clock is 50MHz. There are two ways for loading, JTAG mode and AS mode. The configuration device is EPCS1SI.In the fourth chapter of my thesis, I designed a controller of CAN-bus. I analyzed the function of a CAN-bus controller SJA1000, which is made by PHILIPS, and programmed the frame for my design by using the HDL language. I also introduced the VerilogHDL language and explained how to use the software of Quartusâ…¡. In the meanwhile, I described the BTL (Bit Timing Logic), BSP (Bit Stream Process), CRC (Cyclic Redundancy Check), ACF (Acceptance Filtering), FIFO buffer and all kinds of registers. I introduced the principle of CRC and ACF as well. I demonstrated how to achieve the functions and how to achieve by VerilogHDL, then provided the simulation waves. However, in this paper the modules of BTL and BSP were not studied deeply enough, and in the future we need to do more research work.