FPGA Design And Implementation Of Entropy Codecs In Image Compression System

With the development of teconologies of mobile ,multimedia,internet,communication,and image scaning teconogies,and also the higher and higher requirement for the resolution &quanlity of image,it's hard to meet the real-time requirement of image & vedio copression sysytems by software.So it is to urged to implement compression system by hardware.And In most of the image compression systems,there are entropy encoder following the transformation unit and the quantitier.So Hardware design of parallel Entrpy codes can be wildly used in real-time image compression &vedio compression systems. In this assay, we explore the design of parallel Entrpy codes with "the Satellite video compression"as the background, and the hardware implementation of Entrpy codes is provided. The design of Huffman encoder and decoder are the key parts of the codes. In the design of parallel huffman encoder,we improved the control logic of the packing unit to avoid the error coursed by data missing.And in the design of parallel huffman decoder ,we make full use of the monotony and continuity of the regulated Huffman code ,transforming the parttern mating of decoding to arithmetic opration ,highly decrease the number of memory unit and increasing efficiency and speed of decoding process. The Huffman encoder is linked with the DPCM (processing data of DC sub-band) and run-length encoder (processing data of AC sub-band) to compress the data output by quantitizer after DWT .And The Huffman decoder is linked with the DPCM decoder (processing data of DC sub-band) and run-length decoder (processing data of AC sub-band) to decompress the compressed data and output to quantitier, then to I DWT unit to get back the image. The design of system of RTL Level is discripted by verilog HDL in the top-down way. According to the STA of Quartus II, f max of the entropy encoder is 127M, and timing simulation implies that it work right at the clock 62.5M. And entropy encoder can work right at the clock 62.5M, with the throughout of 2500Mbps. After simulation, complying, mapping and routing, the design is downloaded to the FPGA chip, it also works right and get the right result. Simulation & FPGA validation imply that the design can meet the functional and timing requirent of the project.