Research On Evaluation Methods With Chip Verification Of Approximate Computing System For Binary Weight Neural Network

With the development of the artificial intelligence(AI)techniques in advanced technology and industry,the artificial neural networks(ANNs),regarded as the key algorithms of AI,are widely and rapidly used in cloud computing and edge computing.For the massive applications,the keywords spotting(KWS)is one of the most important interface for smart human-machine interaction,and for the hardware implementations,the real-time response and low-power consumption requirements are critical.Based on the resilience features of ANNs,approximate computing is widely adopting in lowpower ANN acceleration systems in multiple levels,from the software/algorithm design of ANNs,the hardware design of architectures,to the implementations of circuits.As the approximate computing techniques are optimizing hardware consumption at the cost of system accuracy loss,the tradeoff between the approximate computing quality and the hardware resources is very important.One of the key issues to design a high efficient ANN approximate computing system is to innovate a systematic evaluation and estimation approach,which can consider the approximation in algorithm level,the architecture level,and the circuit level.However,the researches mainly focus on the approximate unit evaluation;the evaluation for system is still in lack.The neural network systems are also in great need of the systematic evaluation method.In this thesis,the low-power and high energy-efficiency system for KWS is taken as the implementation.The approach to design an approximate computing system for binary-weight neural networks(BWNNs)is the main research work.The quality model based systematic evaluation and estimation approaches are the key technologies to optimize the BWNN system.To study the systematic approach and the modelling methods,the conventional processing unit modeling methods are analyzed further and extended more.The final proposed systematic evaluation approach can help optimize the BWNN acceleration system for KWS and the chip design.Finally,the optimized design is fabricated under 22 nm ULL COMS technology,and the approach is validated along with the performance of the KWS processor.The main contributions of the thesis are as follows:(1)In this thesis,the computing qualities of the parameterized approximate computing unit and the composite approximate computing module are modeled analytically,including the models for approximate addition units,the approximate noise transmission model for linear datapath,and the parameterized quality model for composite approximate module.Based on the analysis on the kernel algorithms of BWNNs,the relations between the key processing units and the final output computing qualities are qualified and modeled,which provides the basis for the following systematic approach;(2)A systematic quality evaluation approach is proposed to estimate the BWNN system based on approximate computing techniques.Based on the parameterized quality model for approximate units,the approximate noise based datapath-related approximation model can consider the approximate noises from each design level as a part of system error and analyze the system error level by level.By this approach,the thesis minimizes the reduction of the evaluation accuracy caused by the propagation of approximate noise between algorithms,architectures and circuits;(3)Based on the system accuracy evaluation framework,the keyword speech recognition is used as a specific application case.The binary neural network acceleration chip has been designed and optimized.The approximate calculation unit is applied to the Mel frequency cepstral coefficient filter(MFCC)module for keyword speech feature extraction and the neural network acceleration module for keyword speech classification and recognition,and based on the system.The optimization framework fully optimizes and explores the design parameters.At the same time,with this framework,an optimization scheme for the real-time dynamic precision control mechanism of the approximate calculation array is proposed,which further improves the energy efficiency of the system.In order to validate the proposed neural network approximate circuit design approach and the optimization effects,the proposed BWNN accelerator is fabricated under TSMC 22 nm ULL CMOS process,in order to achieve high energy-efficiency system.Compared with the estimated forecasted system accuracy by the proposed systematic evaluation approach,the absolute value of the accuracy difference is within 5%,and the relative value is within 7%.To be specific,the system working frequency is 250 k Hz,the voltages of the I/O drive,the SRAM blocks,and the logic circuit are 1.8V,0.6V,and 0.39 V,respectively.With the system settings,the proposed accelerator can realize real-time response of 10-keywords(12 classes)recognition.For the chip specifications,the overall power consumption of the chip under the HVT transistor is around 7.9μW,and the power consumption of the keyword speech recognition system is 4.1μW.The chip testing results show that the actual test accuracy of the chip is near the accuracy estimated by the proposed system accuracy evaluation approach.Meanwhile,the chip is capable to be adopted under multiple speech noise scenarios and SNR environments,with high recognition accuracy.Comparing to the state-of-the-art keyword spotting engines,the proposed chip can achieve high accuracy and high energy-efficiency with more background scenes in wider SNR.