Design And Implementation Of A Reconfigurable Architecture For Low-power Keyword Spotting In Multiple Noise Scenarios

With the rapid development of 5G and Internet of Things technology,Keyword Spotting(KWS)has become one of the important development directions in the entire speech recognition field,and it is an important measure to improve the ability of human-computer interaction.Since the speech recognition technology is mainly used in small portable devices such as smart phones and wireless earphones,it is very important to design a keyword spotting processor with certain anti-noise ability,low power consumption,and high recognition accuracy.Based on this,a reconfigurable processing system for low-power keyword recognition based on digital microphones for multi-noise scenes is proposed in this thesis.Based on a typical neural network keyword processing system,the software algorithm and hardware circuit are carefully optimized in order to reduce the power consumption of the keyword processing system as much as possible.The main research work of this thesis includes: 1)A precision adaptive dual-mode speech feature extraction design scheme based on Mel Frequency Cepstrum Coefficient(MFCC)is proposed.The proposed MFCC based on scene complexity can achieve adaptive extraction accuracy at different signal-to-noise ratio levels with low-latency mode switching,reducing the computational cost of the feature extraction module;2)A serial pipeline FFT processing unit is designed with stage by stage customized and optimized,this thesis optimizes the circuit structure and limits the data bit width of each stage,which greatly reduces the memory access power consumption and computing power consumption of the FFT processing unit;3)A ternary weight convolutional neural network architecture is designed with data reuse,controllable sparsity and weight compression,which realizes a reconfigurable PE calculation method,further reduces the complexity and calculation amount of the network module,and significantly reduces the power consumption of the classification module.Based on the TSMC 22 nm CMOS process,a low-power keyword reconfigurable architecture for multi-noise scenarios is implements in this thesis.The simulation results show that: Under a main voltage of 0.72 V and a main frequency of 250 k Hz,the minimum power consumption of the keyword recognition system is only 5.63?W,the macro area is only 0.203mm2,and the keyword recognition accuracy can reach 91.4% in the clean scene;At a 5d B noisy scene,the recognition accuracy is also as high as 84.5%.Compared with the architecture of VLSI 2019,the proposed design can reduce power consumption by 69.2% at the same level of accuracy.