Research On Readout Electronics For SiPM Array In TOF-PET Detectors

Compared to the non-TOF PET,using TOF in PET system is capable of achieving a better imaging quality.Hence,research on TOF-PET have always been a hot topic among the academic and industrial community.In the new generation photon detector SiPM(Si-Photon Multiplier),characteristics like low cost,magnetic compatibility,high gain,fast response are very suitable for TOF-PET.However,the design of the readout electronic of SiPM,which are vital to the overall performance of the TOF-PET system,have always been changeling.The readout electronic of SiPM can be divided into three different functional modules:front-end analog module,energy measurement module and time measurement module.This thesis will carry out research on three different modules in the readout electronic of SiPM for TOF-PET application.TOF-PET technology requires a front-end analog module with features like low power,low noise and large dynamic range.This thesis studies the current mode front-end analog circuit that can meet those requirements,and concludes that the current mode front-end circuit RCGTIA(regulated common gate TIA)is suitable for TOF-PET applications.In this thesis,we designed two ASICs(Application Specific Integrated Circuit)for 64 channel SiPM array readout electronics with RCGTIA as front-end circuit.We named these two ASIC as FES A 1.0 and FES A 1.1.Test showed that,with LYSO and SiPM array as detector module,our ASIC can achieve CTR(coincidence time resolution)less than 400ps and 300ps respectively,which means the RCGTIA designed here can meet the requirement of time accuracy in TOF-PET.Instead of studying conventional energy measurement scheme using high speed ADC,the thesis will carry out studies focusing on TOT methods.The TOT methods can achieve energy measurement module with simpler circuits and lower power consumption,in the cost of accuracy.To solve the accuracy problem,this thesis designed the TOT scheme with linear discharge structure.With this improvement,the energy measurement modules in this thesis have simple structure,low power consumption and good accuracy.we implement the energy measurement modules Using PCB and 0.18 CMOS technology respectively,test results showed the modules can achieve good performances.The essential of the time measurement module is the design of the TDCs(time-to-digital convertor).Recently,TDCs based on FPGA have been favored by researchers because of the short develop time,high time precision,and the feasibility of digital integration.This thesis proposed a decomposition method that is 100%bubble proof.Unlike other bubble proof method,the decomposition method is also resource efficient and fast.Thanks to these features,test results showed TDC designs based on decomposition can achieve high time precision(<10ps),large time measurement range and low hardware resource cost.The thesis also proposed few TDC designs based on wave union A and fold structure that can maintain the high performances with low hardware resource cost.This thesis also discusses the TDC design in CMOS technology,which has always been a research hotspot in the recent years.CMOS technology enables features like more flexibility,lower power consumption and lower cost in the TDC design.This thesis focused on the TDC design based on DLL and proposed a design method to minimize the power consumption of the DLL.The design method can lower the clock frequency of the DLL dramatically,without changing the delay and amount of the unit in the voltage control delay line(VCDL),hence the power consumption is lowered dramatically.This thesis also studies the structure of two-stage TDC for a better time resolution.After the first interpolation enabled by VCDL,the second interpolation will be conducted by amplifying the quantization error from the first interpolation.The simulation showed the two-stage TDC designed in this thesis can achieve time resolution with 14ps LSB and static power less than 0.5mW.With the technology the thesis studied before,two SIPM array readout ASICs,FES A 1.0 and FES A 1.1,had been manufactured with 0.18 um CMOS technology.They can readout signals from 64 channel SiPM array.Rows&Columns multiplexing scheme is used in the ASIC to save numbers of the output I/O pin.Both ASIC used RCGTIA as their analog front-end and linear discharge circuits as their energy measurement scheme.PCB is designed to evaluate performance of ASIC designed in the thesis.Test result showed with LYSO and SiPM array as detector module,FES A 1.0 can achieve 12%energy resolution and CTR less than 400ps with 2.1 mW per channel.FESA1.1 has higher integration level because of the implementation of the auxiliary circuits like comparator,DAC,SPI in FES A 1.1.Moreover,RCGTIA in the FES A 1.1 can achieve higher bandwidth and lower noise;energy measurement modules in the FES A 1.1 have better resolution when the signal amplitudes are small.Test results showed that FES A 1.1 can achieve 12%energy resolution and CTR less than 300ps with 2.2 mW per channel.Benefited from a better resolution of small signals,FESA1.1 can achieve 2D spatial resolution with 1.02mm(1.02mm*1.02mm*10mm LYSO array is used).FESA1.1 can achieve good time,energy,and spatial resolution with low power consumptions,which makes it suitable for TOF-PET application.