| RF microsystem adopts advanced packaging technology to integrate high-density RF,photoelectric,digital,energy,and other functions.It has the characteristics of miniaturization,multifunction,and even low power consumption and low cost.It has wide application prospects in radar detection,communication,electronic warfare,reconnaissance,and other fields.However,further miniaturization of RF microsystems brings new challenges to the integrated design of complex function units,especially the mismatched interference between cascade RF units,the electro-thermal coupling between chips,process fluctuation effects in chips fabrications.These factors result in a long design period and a low yield of RF microsystems.They should be well considered in RF microsystems design.In order to meet the requirements of the rapid iterative design of complex systems,the multi-physical field collaborative design method,which is based on reusable and highly trusted IP(Intellectual Property)core,has become a research hotspot of microsystem design methodology.An accurate chip IP model is the key to system-level simulation evaluation and optimization design of chip in the system application.However,compared with the IP modeling of more mature digital and analog chips,IP modeling of RF chips is still in the exploratory stage,and its main difficulties are as follows:(1)Not only the input/output function but also the input/output mismatch,nonlinear characteristics,high-frequency noise,and many other characteristics should be considered in the model;(2)Due to the difficulty in process control during the RF chip fabrication,the performance of IP from different Foundry varies greatly and is difficult to be commonly used.Therefore,the technical characteristics should be taken into consideration in all of the output characteristics;(3)The electro-thermal coupling effect of transistors in the chip is prominent,especially the further application of gallium nitride(GaN)devices in RF Microsystems in recent years,which results in the obvious decline of the accuracy of traditional models.Therefore,establishing an accurate and highly reliable RF chip IP model has become a significant challenge in RF Microsystems simulation and designs.In this dissertation,passive electromagnetic(EM)model and transistor equivalent circuit model are implemented to study the modeling techniques of key components in GaN RF front-end including low noise amplifier IP and power amplifier IP,especially the physical-based nonlinear and noise models,modeling of process fluctuation and thermoelectric coupling effect of GaN HEMT devices.The main research contents include:1.Research on chip IP modeling method of GaN low noise amplifier.Traditional GaN HEMT noise models are not able to predict noise performance under different ambient temperatures,which may result in the limitation of chip IPs application.In order to solve this problem,a physical-based noise model without fitting parameters is proposed in this dissertation at first.The model was deduced using the zone division theory of transistors.An improved boundary potential calculation method was implemented to obtain the expressions of intrinsic noise.Owing to this modification,the accuracy of the intrinsic gate and drain noise models are well improved.Then,the dependence of ambient temperature is considered in key physical parameters such as Schottky barrier height,electron mobility,and electron saturation velocity.This contributes to the accurate prediction of transistor noise characteristics ranging from-55 ? to 125 ?.The accuracy of this model is higher than 83.69 %.Finally,the noise model is embedded in a 2-6 GHz low noise amplifier.Compared with the commercial process design kit(PDK)model,the accuracy of noise coefficient and gain of the established IP model in the frequency band is improved by 11.95 % and 17.86 %,respectively.2.Research on IP modeling method of GaN power amplifier chip.In the traditional transistor trapping effect model,the lack of considering quiescent drain bias will result in the inaccurate prediction of pulsed I-V characteristics under high quiescent drain bias.Also,the I-V kink effect is unable to be characterized based on traditional modeling methods.In order to solve the problems above,an improved trap model is proposed in this dissertation.The dependence of quiescent drain bias is considered in dynamic control potential.Owing to this improvement,the accuracy of the current model is improved by nearly 10 % in the whole range of bias.Then,the I-V kink effect modeling method was studied.A physical-based I-V kink model was established based on the Shockley-Read-Hall(SRH)model and the impact ionization model.This model can further improve the accuracy of the current model.Finally,compared with the commercial PDK model,the accuracy of the scalable model established based on the above method is improved by 19.32 %.After embedding this model into a 2-6 GHz PA,the accuracy of Pout,gain,and PAE of the established chip IP model in the frequency band can reach up to 95.28 %,86.51 %,and 86.64 %,respectively.Another 2-18 GHz PA verification shows that the improvement of the accuracy of PAE is 28.41 %.3.Research on statistical large-signal model and optimization design method of circuit yield.The traditional large-signal model is unable to predict the process fluctuation.In order to solve the problem,an improved factor analysis model is proposed at first to characterize the statistical distribution of key physical parameters.After implementing them into the large-signal model,the statistical large-signal model can be established to associate the statistical characteristics with nonlinear characteristics of transistors.Then,a yield optimization design method was proposed based on the model,which can further realize the yield optimization design on the basis of the traditional maximum power or efficiency design method.Finally,the results of a32-38 GHz 15 W power amplifier chip show that the accuracy of the mean and standard deviation of the output are higher than 98 % and 80 %,respectively.In addition,the yield calculation results show that the circuit yield can be improved by nearly 13 %using the proposed method in this dissertation compared with the traditional one.4.Research on applications of GaN chip IP model.In order to explore the role of the chip IP model in complex circuit design and performance evaluation in different packaging environments,a 2-6 GHz GaN multi-functional chip is employed for integrated application verification of the established low noise amplifier IP model and power amplifier IP model in this dissertation.Compared with the commercial PDK model,the accuracy of noise characteristics of receiving branch is improved by 8.4 %for the established model.For further validation of the prediction ability of IP model in packaging environment,the implementation method of IP model in commercial EDA simulation software was studied.The electro-thermal simulation modeling and the construction of the chip IP library were also realized.Simulation results show that the chip IP model can effectively predict the ambient temperature effects of output performance in the different packaging environments.The RF chip IP modeling method and the circuit yield optimization design method proposed in this dissertation have great theoretical significance and engineering application value for the development of the GaN RF microsystem. |
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