Research On Several Key Issues Of Low Power SiC Integrated Module

Among various new packaging methods of SiC MOSFETs,power module with integrated gate drivers,ceramic capacitors can greatly reduce power loop and driving loop parasitic inductances.It can help realize fast switching of SiC devices,low propagation control,and further to reduce loss,elevate frequency and systems'power density.This dissertation focuses on low power SiC integrated module,researching and analyzing several key issues from aspects of modules'thermal performance,electrical performance,protection and control functions.Thermal performance of the module is closely related to its loss.Switching loss is the most complicated part among losses of integrated power module(IPM).Due to the compact structure of SiC IPM,it is difficult to calculate loss accurately by measuring its switching waveforms.So,this dissertation establishes a dynamic model to rapidly assess switching loss,based on parasitic inductances,driving voltage,resistance from real prototype and transfer characteristics,parasitic capacitances of the power devices.When modelling,this dissertation fully considers SiC MOSFETs'transfer characteristics under high drain-source voltage(v_ds),affected by short-channel effects,and dynamic transfer capacitance during switching periods.These characteristics are measured by proposed methods and compared with information from traditional datasheet about their differences and influence.The final improved model can predict switching waveforms more accurately,and elevates accuracy of loss evaluation.Considering electrical performance,the complicated electromagnetic environment inside SiC IPM will interfere the driving circuit and cause abnormal conditions of power devices.During switching transient,extremely large dv/dt generated at midpoint of the half bridge during switching period is coupled to the input pins of gate drivers through parasitic capacitances of DBC substrate,causing false switching.This dissertation establishes models to analyze these interferences.According to the model,these interferences may cause problems such as false turn-on or even shoot-through when switching speed is high enough.Based on the model,a series of interference suppressing methods are proposed and compared.It is proved that by introducing a shielding layer,the interference effect caused by dv/dt can be eliminated without lowering normal switching speed of power device.In order to further improve performance and reliability of SiC IPM,this dissertation explores the possibility of integrating current sampling inside the module.This dissertation takes advantages of tunnel magnetoresistance(TMR)sensors,such as small footprint,high bandwidth,low propagation,and analyzes its application in SiC IPM,expecting fast response of short-circuit protection,over-current and peak current detections.In real applications,varied current generates induced electromotive force in the output loop of TMR sensor and voltage fluctuation in the adjacent conductors will caused interference inside the TMR sensor through electric field,both of which interfere the actual current sampling.By theory analysis and experiment verifications,it is recommended to minimize the output loop of TMR as small as possible and increase the signal-to-noise ratio.It is also suggested placing TMR around conductors with small voltage changes and adding comb-shaped shielding ground to reduce influence of the interference.The optimized sampling method of TMR is applied in a totem-pole PFC circuit for zero current detection(ZCD).Sampling waveforms of TMR reflect the measured current accurately and can realize turn-off of the free-wheeling SiC MOSFET at zero current timepoint within whole ac voltage range.At last,the optimized sampling method of TMR is used to measure current inside the SiC IPM,from double pulse test to buck converter.This optimized circuit can measure device's current accurately and provides a good design guidance for current sampling integration inside SiC IPM.