Research On High-precision Time-to-digital Conversion Circuit For GM Single Photon Detector

Single-photon detection has broad application prospects in the fields of lidar threedimensional imaging,fluorescence lifetime imaging,and laser communication.The avalanche photodiode working in the Geiger area can trigger a diode avalanche by a single photon and generate an avalanche current.It is a very good single-photon device.The single-photon detection system based on the focal plane of the Geiger Avalanche Photodiode(GM-APD)has the characteristics of high sensitivity,long detection distance,and high ranging accuracy.It realizes distance detection by measuring photon flight time.The readout circuit(ROIC)of the integrated time-to-digital conversion circuit(Time to Digital,TDC)and the GM-APD array can accurately measure the photon flight time.The timing accuracy of TDC determines the ranging accuracy of the entire detection system,so the time-to-digital conversion circuit is the key module in the readout circuit.In Ga As APD detector can be applied to the short-wave infrared band and has the characteristics of high detection efficiency,low cooling requirements,fast response speed,and safety to the human eye.Under the application background of In Ga As GMAPD single-photon detection three-dimensional imaging and three-dimensional ranging system,combined with the application requirements of high photon flight time timing accuracy,large timing range,and high working frame rate,the paper is applied to long-line array/area array GM-Research on high-precision time-to-digital conversion circuit of APD focal plane.The details are as follows:(1)For linear applications,a two-stage solution is adopted to design a 128×4 lowpower ultra-high-precision linear TDC.The TDC meets 50 ?m center distance applications.The low segment TDC uses Cyclic algorithm and Nutt interpolation technology to amplify and quantify the remaining time error multiple times within a detection frame.It can achieve ultra-high-precision timing at a reference clock frequency of 100 MHz.The high segment TDC uses a linear feedback shift register to extend the timing range The actual measurement results show that the TDC can achieve a time resolution of 78.3 ps and the power consumption is 30.7 m W at a working frame frequency of 10 k Hz.Linear TDC can be expanded to a larger scale.(2)For array applications,a local shared three-stage structure is adopted to design a 64×64 low-error high-precision array TDC.The TDC meets 100 ?m center distance applications.Low segment is shared by full array.TDC achieve sub-nanosecond time resolution by multi-phase clock.The low and middle segments greatly reduce the probability of latching error codes through delayed sampling.Linearity is improved.The actual test results show that this TDC achieves a time resolution of 0.5 ns,-0.4 LSB<DNL <0.4 LSB,and achieves a low bit error rate.(3)The multi-stage split-phase clock of array-type TDC is generated by DLL/PLL.Multi-stage split-phase clock can break the limit of the reference clock cycle and realize high-precision timing.The global clock signal enters each pixel unit through the Hshaped clock network to improve the timing consistency of each pixel.The actual measurement and post-simulation results show that within the DLL lock range,the phase noise is lower than-127 d Bc/Hz @ 1 MHz,the RMS jitter is lower than 3 ps.The PLL phase noise is lower than-117 d Bc/Hz @ 1 MHz.The RMS jitter is less than 4 ps.The signal delay error of each node after the clock tree simulation is less than 1%,which meets the application requirements.