The Research On Electrothermal Characteristics And Model Of Nanosheet Gate-all-around Field Effect Transistor(NS-GAAFET)

With rapid development of the integrated circuit industry,the nanosheet gate-all-around field effect transistor(NS-GAAFET)with the excellent gate controllability and tunable channel width,has emerged as the convictive candidate to replace the FinFET as the core device beyond 5 nm technology node.However,limited by the confined three-dimensional stacked structure,the introduction of the germanium-silicon and the degradation of silicon thermal conductivity in nanoscale,the heat dissipation capacity of NS-GAAFET is poor,causing the accumulation of the heat and exacerbating the self-heating effects(SHEs).Meanwhile,the higher power density is induced by the improvement of chip integration,with the characteristic dimension of core devices shrinking.The electrical characteristic and reliability issues are worsened by rising temperature,and the performance and working life of the chip are further affected.As a result,the research on electrothermal characteristics of NS-GAAFET has important guiding significance for the design of integrated circuits with high performance and reliability in further 2-5 nm technology node.Focused on the electrothermal coupling optimization design of NS-GAAFET in deep-nanometer technology node,this thesis carries out research from the realization of electrothermal coupling calculation,structural dependence of the electrical and thermal characteristics,optimization of structure,modeling and calculation method of thermal coupling separation,channel thermal iterative algorithm,extraction of compact model and analysis of the circuit performance.The major research contents and results are as follows:Firstly,the structure of NS-GAAFET in 5 nm technology node is established,and then the calibration with experimental data and the structural dependence of the electrothermal performance are performed.The numerical results show that:(1)due to the lower thermal conductivity of germanium-silicon,the SHEs in the P-type devices are more severe than that in N-type devices,and the peak working temperature of P-type device is 44.16 K higher than of N-type device,resulting in a twice increase of the on-state current degradation under the saturated working conditions;(2)the increase of the channel width,channel thickness and effective channel length,the decreasing number of the stacked channels,the raised thermal conductivity of the materials in spacer region,the rising ambient temperature and the appropriately increasing density of the VIA in the local back-end-of-line interconnection region on the side of drain side are beneficial to improve the thermal performance to an extreme.Secondly,a novel vertical combo spacer structure including the inner spacer with high thermal conductivity and the outer spacer with high permittivity is proposed to realize the electro-thermal tradeoff optimization of multi-channels NS-GAAFET in 5nm technology node.The numerical results indicate that,compared to the conventional single-spacer device with HfO₂ spacer,the combo spacer device with the 3 nm thick inner spacer,the on-and off-state current ratio increases 82.27%with the 14.29%decrease in thermal resistance for N-type device,and the variation of 42.67%and-45.35% are observed in the on-and off-state current ratio and thermal resistance of P-type device,respectively.It is proved that the vertical combo devices can optimize the thermal performance and improve the switching characteristics of NS-GAAFET.Thirdly,modeling and calculation method of thermal coupling separation and thermal iterative algorithm are presented in this thesis.The results show that:(1)based on the thermal resistance representing for Joule Heat and thermal coupling separated from single and dual silicon channel layer structure,the maximum error between the temperature prediction and numerical calculation are 2.7% and 4.1% in N-type and P-type devices,respectively;(2)the reduced space between channels,the use of SOI substrate and the increasing number of stacked channels will deteriorate the thermal coupling effect;(3)based on the thermal iterative algorithm,the errors between formula model calculation results and TCAD are 5.46% and 5.89%,respectively for N-type devices with bulk and SOI substrate,which verifying the accuracy of the formula model.Fourthly,based on the electrothermal numerical results and BSIM-CMG compact model,the extraction flows of the electrical and thermal parameters for NS-GAAFET are established and the electrothermal analysis of basic logic cell and SRAM cell are performed.The calculation results reveal that:(1)the extracted error of the on-state current is 0.002%and 0.007%,and the error of peak working temperature is 0.002%and 0.007%,respectively in N-type and P-type device;(2)the maximum DC gain of CMOS inverter is degenerated by 16.23%due to the SHEs,and the degradation of the propagation delay is enhanced with the increase of load capacitance;(3)affected by the charge or discharge of load capacitance in the logic flip,the rising time and falling time of the logic circuit are all deteriorated induced by SHEs;(4)due to the degradation of performance in transfer transistor induced by the SHEs,the write delay time of SRAM cell suffers from the most pronounced influence,with the degradation of 11.3%.The work of this thesis involved the analysis of the electrothermal characteristics,the optimization of the device structure,modeling and calculation method of thermal coupling separation,thermal iterative algorithm and the extraction of compact model for the NS-GAAFET in the deep-nanometer technology node,which has important industrial application value for optimization of electrical and thermal characteristics of NS-GAAFET,the electrothermal co-simulation design and integrated circuit with high performance and reliability.