Electrical Characteristics And Its Control Method Of Paralleled Silicon Carbide MOSFET Chips

Power semiconductor devices are the core components for manufacturing power electronic equipment.The limits of physical properties of the traditional silicon materials,such as electron saturation drift velocity,critical breakdown field,thermal conductivity and energy gap,hinder the improvement of performance limit of silicon-based power devices.This restricts the development of the power electronic equipments towards higher efficiency,higher power density and higher operating temperature.Therefore,it is of great significance to develop silicon carbide(SiC)materials with higher limits of physical properties,SiC-based devices and SiC module for improving the performance of power electronic equipments.Despite that the exhibiting performance is closer to ideal switches than silicon-based IGBT devices,SiC devices are presently facing great challenges.Currently,the current rating of the commercial single-chip SiC MOSFET device is not sufficient for the requirements of high-power applications.Developing of power module packages with parallel-connected multi-chips is still the path mainly taken to realize SiC-based devices that can handle high power applications.However,the paralleled chips in a SiC power module will suffer the large voltage overshoot and current imbalance during high-speed switching period,due to the electrical parameters spread of SiC MOSFET chips and the asymmetrical distribution of parasitic parameters of module package.Inspired by the urgent demand for the development of SiC power module with parallel-connected multi-chips,this thesis focuses on SiC MOSFET multi-chips packaging issues and systematically studies the electrical characteristics and its control methods for paralleled SiC MOSFET chips.First,the switching characteristics of a single-chip SiC MOSFET device were investigated.A piecewise analytical method for switching characteristic,considering the influence of parasitic parameters,was presented.Then,the relationships between the turn-off voltage overshoot,the turn-on current overshoot,the switching oscillation frequency and parasitic parameters were derived,respectively.This provided a method for extracting the parasitic inductance in the power loop of power module.Futhermore,A general test system was designed and built for evaluating the switching characteristics of single-chip SiC MOSFET device,multiple single-chip devices in parallel-connection and power module with parallel-connected multi-chips.The voltage,current and switching loss of single-chip SiC MOSFET devices over the range of 25?-150? were tested.The key parasitic parameters affecting turn-on and turn-off transient characteristics in the test system were experimentally studied,which verified the previously derived correlation.Moreover,the maximum peak shifting phenomenon of turn-off voltage and its initial mechanism were revealed through the combination of experiment and simulation analysis.Second,the influence of chip's electrical parameters on current distribution of paralleled SiC MOSFETs and the current balancing methods were studied.The spread of electrical parameters of SiC MOSFET was analyzed statistically.Then,the influence of different electrical parameters on current distribution characteristics was studied.The key parameters characterizing the current distribution were obtained.Furthermore,a chip classification method based on transfer curves was proposed.A simulation circuit model was established to analyse the sensitivity of current imbalance to the distance coefficient of transfer curves(DCTC).It was found that the transient current imbalance of paralleled devices has a linear positive correlation with DCTC.The sensitive of DCTC to junction temperature were also studied.It was found that DCTC has a low sensitivity to junction temperature.Moreover,a hierarchical clustering algorithm based on DCTC was developed to realize the automatic classification of single-chip devices to meet the requirements of current imbalance control.An experimental platform with circular layout was built to carry out switching test for paralleled multiple single-chip devices.It is verified that the current distribution can be improved through deploying the classification algorithm to identify the devices to parallel.Third,the influence mechanisms of common impedance conduction coupling and mutual inductance coupling on current distribution of paralleled SiC MOSFETs were studied.The conduction coupling path of the common branch impedance between power circuit and driver circuit of paralleled chips with common source connection,Kelvin source connection,and hybrid source connection,were analyzed,respectively.The influence of source parasitic inductance on transient current distribution of paralleled chips were revealed.The relationships of current imbalance of paralleled chips with three different kinds of source connection types and source parasitic inductance were derived,respectively.Furthermore,the typical packaging layout of the commercial multi-chips power module with parallel-connected SiC MOSFETs was investigated.The influence mechanisms of the common branch impedance coupling among the power circuits and the mutual inductance coupling among chips and between chips and busbar on current distribution of paralleled chips in a power module were revealed.These provided a theoretical basis for optimizing the packaging layout design of multi-chips power module with parallel-connected SiC MOSFETs.Finally,the control method of electrical characteristics of multi-chips power module with parallel-connected SiC MOSFETs was studied.A low-profile packaging structure with multiple substrates and leading-out terminals was proposed.Then,a 1.2kV/300A SiC power module based on this packaging structure was designed,which reduces the parasitic inductance in power loop and drive loop and eliminates the asymmetry of coupling effect of common branches and mutual inductance effect among the power circuits of paralleled chips.The multiple input-output ports circuit models of power module were established.The simulation results verified that paralleled chips in the proposed module have a lower voltage overshoot and a more balanced current distribution.The packaging process of SiC power module was also explored and improved to reduce the complexity of gate bonding and terminals'welding process.A test platform was built for evaluating switching characteristic of SiC power module.The parasitic inductances in the power loops of the commercial and proposed modules were extracted,respectively.It was verified that switching performance of the proposed module is superior to that of the commercial module.