| Discrete Event Simulation (DES) is a widely used simulation methodology for systems where changes of state occur at discrete times. Examples include the simulation of computer and telecommunication systems, control systems, and biological simulations. Parallel Discrete Event Simulation (PDES) harnesses parallel processing to improve the performance and capacity of DES, supporting larger and more detailed models, or more scenarios. However, the performance and scalability of PDES is often limited by communication latencies and overheads.;The emergence of multi-core processors and their expected evolution into many-cores offers the promise of low latency communication and tight memory integration between cores. These properties can significantly improve the performance of PDES in such environments. In this dissertation, we make two contributions. First, we design and optimize a multi-threaded PDES simulator for multi-cores. We show that our proposed simulator can achieve significant performance improvement. Furthermore, to support larger-scale simulations, we extend the proposed simulator on a cluster of multi-cores (CMs). We demonstrate that the communication overheads across the network impose a substantial bottleneck on PDES. To address this problem, we propose three optimizations: message consolidation and routing, infrequent polling and latency-sensitive model partitioning. Second, most conventional PDES algorithms were developed under the assumption of a homogeneous environment with no interference from other co-located applications. In practice, however, it is common that some applications from other users run concurrently with PDES, leading to slowdowns. We present a metric to quantify PDES performance in the presence of such interference. We then show that the actual slowdown experienced by PDES far exceeds the expected one. Consequently, we focus on developing solutions to tolerate interference for PDES. In particular, we first propose an application-level approach to PDES resilience by using alternative simulation scheduling and mapping algorithms. In addition, we also investigate a hybrid interference resilience approach, which combines the proposed application-level scheme with appropriate support from the OS scheduler. |
