| Modern LSI and VLSI designers make frequent use of pass transistors in the design of digital circuits. Pass logic has attractive features which include no static d.c. power dissipation, high density relative to layout, high and symmetric drive capability and high operating speed. The major disadvantage to pass logic is that no formal design techniques have been developed that are easy to use. Therefore, the design of pass logic networks is currently being done mostly by intuition, experience, and perseverance.; This dissertation is divided into four parts. First, a unified switching theory is developed which is centered around a set of simplification theorems and identities, which could be directly applied in designing minimal pass networks. Second, a graphical approach to pass logic design is developed utilizing the traditional Karnaugh map in a way that is closely related to implementing regular gate networks, making an easy adjustment from realizing gate logic to pass logic. Third, an algorithmic approach similar to the Quine-McCluskey tabular approach is developed which is directed towards the simplification of complex networks of more than six variables. The last part of the work is focussed on the development of fault detection techniques for pass transistor networks. Theorems are developed that allow for test generation of an arbitrary pass network. Moreover, structures are defined that allow for complete fault coverage. |
