Performance evaluation of RISC based architectures for image processing

The Reduced Instruction Set Computer (RISC) approach has primarily targeted general purpose computations. The success of RISCs has motivated this research on their adequacy for special purpose applications, particularly Image Processing (IP). First, a detailed investigation of the computational model of image processing has been performed. The focus is given to the anatomy of IP-operations, the statistics of the frequently used instructions and addressing modes and the detection of the major sources of enhanced features for IP-architectures. A general simulation model for RISC-architectures has been developed using NETWORK II.5 simulation language. A number of simulation enhancements have been made to adapt the use of NETWORK II.5 towards the micro-architectural simulation level. A number of alternative enhanced features have been evaluated using four modified versions of Berkely RISC II at both micro-architecture and system level by using the simulation methodology developed.;Important observations have been made from the simulation analysis based on a proposed cost factor criterion whose main components cover the relevant RISC constraints as well as the important performance metrics of IP-workloads. The statistical program measurements have indicated a sharp skew in favor of a reduced number of simple instructions and the need for a few special constructs to enhance the operand multiplicity as well as the window-type operations. The off-chip to on chip memory access ratio has indicated relatively high values (about 25%-30%). Raising the architectural level of the instruction set of the enhanced models to support directly some frequent operations such as multiple-load, window-set up, raster-scan and X-Y address calculation has indicated a significant impact on the overall performance figures. The enhanced models have indicated a speed-up factor of 4-15 when compared to the non-enhanced. However, adding to the complexity of the hardware design slows down the instruction cycle of the non-primitive instructions. The analysis has indicated an estimated upper bound of 1.82 on the Instruction Cycle Penalty (ICP) or overhead delay in order to guarantee an overall performance gain of the enhanced models. The measurements as well as the evaluation methods of this work establish a useful background material on the statistics made on IP-programs and the performance evaluation of different architectural aspects. (Abstract shortened with permission of author.).