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Negative resistance loss compensation in distributed amplifier design

Posted on:1989-02-18Degree:Ph.DType:Dissertation
University:The University of Wisconsin - MadisonCandidate:Deibele, StevenFull Text:PDF
GTID:1478390017954862Subject:Engineering
Abstract/Summary:
A high gain common gate FET can present at its drain a broadband impedance characterized by a (frequency dependent) negative resistance and a capacitance. Common gate FET circuits that exploit this property, termed "negative resistance circuits," have been examined both theoretically and experimentally. Loading the lossy artificial lines of a distributed amplifier with negative resistance circuits reduces the line attenuations which limit the gain, bandwidth, and maximum output power performances. The result is an increase in the useful number of active devices with a consequent increase in the gain-bandwidth and gain-maximum operating frequency products. Because of its similarities to the negative resistance circuit, the cascode circuit is evaluated for distributed amplification. Several designs employing the common gate FET loss compensating circuit and/or the cascode amplifying circuit are compared to a conventional distributed amplifier optimized for gain-bandwidth product. Simulated gain-maximum operating frequency product increases of 27% to 245% over that of the conventional distributed amplifier are shown. The increases in single stage amplifier gain are often accompanied by proportional increases in maximum output powers.
Keywords/Search Tags:Common gate FET, Negative resistance, Amplifier, Gain
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