A STUDY OF SELF-ALIGNED RECESSED GATE INDIUM-PHOSPHIDE AND INDIUM-GALLIUM - ARSENIDE FIELD-EFFECT TRANSISTORS (FET, OPTOELECTRONICS)

Interest in the compound semiconductors InGaAsP grown lattice-matched to InP substrates has been stimulated by their application for long wavelength optoelectronics. Among all the InGaAsP alloys, both InP and InGaAs have been studied for possible high speed field-effect transistor application because of their high electron mobilities and high peak drift velocities, and the potential integration of these transistors with photonic devices. In the implementation of high performance field-effect transistors fully utilizing the excellent material transport properties, it is important to minimize the parasitic resistance, and a self-aligned recessed gate structure is desirable. In this work we have designed, fabricated and characterized three different types of self-aligned recessed gate field-effect transistors using InP and InGaAs.;In the design of the submicrometer self-aligned recessed gate InGaAs MISFET, a combination of angle evaporation for submicrometer pattern definition and sputter etching/wet chemical etching for channel recess was used to implement this FET structure. Transconductance as high as 300mS/mm has been observed for these silicon nitride insulated gate MISFET with 0.5 m gate length. This is the highest transconductance ever reported for InGaAs FETs.;In the design of the enhanced Schottky gate InGaAs FET with a self-aligned recessed gate structure, a thin silicon oxide layer was introduced between the gate metal and the channel semiconductor layer to reduce the gate leakage current. These 1.5(mu)m enhanced Schottky gate FETs showed very good pinch-off characteristics with transconductances of 150mS/mm, which are higher than that of GaAs MESFET with the same gate length.;In the design of the self-aligned recessed gate InP MESFET, the anisotropic and selective etching properties of InP/InGaAsP system were utilized to alleviate the difficulties associated with channel recess and gate aligned. A 1(mu)m Al gate InP MESFET with measured transconductance (TURN)100mS/mm is demonstrated using this technique. The technique is also shown to be capable of producing submicrometer gate lengths with conventional optical lithography. In addition, the FET channel thickness is predetermined during epitaxial growth. This feature greatly simplifies the fabrication process and should lead to a better uniformity in device characteristics over the entire wafer.