Computer-aided design of high-throughput digital filters and testing of iterative logic arrays

Application-specific computer-aided design (ASCAD) tools are developed for producing very high-throughput FIR and IIR filters. This dissertation gives a detailed description of the CAD tools, and presents algorithmic and architectural insight into the digital filters studied. Block pipelined algorithms designed for these filters are implemented with bit-level systolic architectures, which guarantee high throughput rates, and high regularity of circuit layout. Regular circuit layout makes cell placement and wire routing simple. Because the tools are application-specific, they are very high level CAD tools.;For an FIR filter, an engineer only needs to specify the filter order ;Testing the filter circuits also is discussed. A scan path is integrated into the IIR filter circuit to improve its testability. Motivated by the problems encountered in testing the filter circuits, combinational iterative logic array (ILA) testing is studied. First, a variety of conditions are presented which, when met, guarantee an upper bound on the size of the test set for the ILA under consideration. Second, techniques are presented for designing optimally testable ILAs. The arrays treated are, in some cases, more general than those reported by other researchers: They include multidimensional and inhomogeneous arrays. Octagonally-connected arrays, hexagonally-connected arrays, and bilateral arrays also are discussed. The results indicate that the characteristics of the individual cell functions (e.g., whether they are injective) are a good guide to the test complexity of the overall array. Matrix product, as an example, is shown to have several different optimally testable implementations. The results are useful for combinational and pipelined arrays, and certain systolic arrays.