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A submicron self-aligned gate gallium arsenide MESFET processing technique for MMIC device fabrication

Posted on:1990-06-28Degree:Ph.DType:Dissertation
University:The University of Texas at ArlingtonCandidate:Chen, Chun-YaoFull Text:PDF
GTID:1478390017453978Subject:Engineering
Abstract/Summary:
A self-aligned, recessed T-gate (SART) processing technique is presented here. It does not require a thick active layer like other self-aligned gate (SAG) techniques to allow the recessed gate to sit at some reasonable distance below the source-drain ohmic contact metal. It also does not need high melting point refractory metals. The SART technique offers advantages of simplicity and saturation current adjustability through recessing the channel. It meets the requirement that gate metallization must be made after alloy process. The SART technique combines the recessed channel process and a gate undercut etch to achieve low gate and source resistance. It also offers process control to optimize the spacing between gate and source (or Drain). This technique provides a high yield of working MESFETs. A 2{dollar}mu{dollar}m gate length mask has been used to start with the SART process and the T-gate etch to obtain submicron gate length (0.63{dollar}mu{dollar}m). A SART MESFET with 75 {dollar}mu{dollar}m of gate width was fabricated with MSG up to 16 dB and f{dollar}sb{lcub}rm max{rcub}{dollar} = 60 GHZ.
Keywords/Search Tags:Gate, Technique, Process, SART, Self-aligned
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