| A new InGaAs/GaAs strained-layer heterojunction field-effect transistor (FET) intended for high-speed, low-power digital integrated circuit applications is investigated. The selection of the transistor structure begins with a review of currently available logic design approaches for GaAs integrated circuits. Based on its simplicity and suitability for very-large-scale-integration (VLSI), the direct-coupled FET logic (DCFL) appears to be most suitable. DCFL, however, places demands on FET characteristics which ostensibly could best be met by a junction FET structure. Thus the focus of the dissertation is on the investigation of an anisotype (p-n junction) heterojunction FET (A-HJFET) for GaAs digital logic, taking advantage of the versatility of molecular beam epitaxy (MBE).; The material properties of an A-HJFET, consisting of a 20 nm thick Si-doped n-In{dollar}sb{lcub}0.15{rcub}{dollar}Ga{dollar}sb{lcub}0.85{rcub}{dollar}As and a 60 nm thick Be-doped p{dollar}sp+{dollar}-GaAs separated by a 7.5 nm undoped Al{dollar}sb{lcub}0.35{rcub}{dollar}Ga{dollar}sb{lcub}0.65{rcub}{dollar}As, is examined in terms of strain-induced electronic properties and energy band offsets. A study of strained-layer devices suggests that these structures are metastable and are subject to non-uniform strain relaxation. Although they can be successfully grown by MBE, exposure to high-temperature processing such as rapid thermal annealing may have detrimental effects on device performance and yield.; A low-temperature, self-aligned refractory metal gate processing technology is thus developed in order to compare with the more traditional double ion implantation process. An increased uniformity of device parameters is indeed observed and a transconductance of 250 mS/mm was obtained for a nominal gate length of 1.5 {dollar}mu{dollar}m. In order to compare devices with different gate dimensions and from different processing technologies, a JFET model modified to include electron velocity saturation in the channel is used. The important parameters for DCFL integrated circuits, specifically the threshold voltage, the transconductance parameter, and the noise margin are then characterized. The results of this modeling clearly indicate that devices fabricated with the new low-temperature, self-aligned process is at least as good as those fabricated with a high-temperature process, if the device dimensions and material parameters are identical. Moreover, the A-HJFET also demonstrate the potential for higher speed of operation, larger noise margins, improved uniformity and reproducibility than conventional IFETs and MESFETs. |
