Analysis and design of an all-digital BPSK direct sequence spread spectrum IF receiver

A VLSI architecture design for an all-digital Binary Phase Shift Keyed (BPSK) Direct-Sequence (DS) Spread-Spectrum (SS) IF receiver using an integrated CAD environment is presented. In-depth performance analysis is also given. The receiver design is targeted at a single chip implementation and digital signal processing has been exploited to reduce the cost and to improve the system reliability and performance. The all-digital architecture incorporates a digital Costas loop for carrier recovery and a digital delay-locked loop for clock recovery. For the PN acquisition block, a robust energy detection scheme is proposed to reduce false PN locking states over a broad range of signal-to-noise ratios. The proposed architecture is intended for use in the 902-928 MHz unlicensed spread spectrum radio band. Based on measured results with a test chip, the proposed receiver architecture can achieve a chip rate of a 12.7 Mchips/sec. This implies a 100 kbps data rate with 127 chips/bit for use in wireless local area network (WLAN) applications. For secure speech transmission, a 16 Kbps data rate with at least 512 chips/bit can be achieved. The IF frequency is chosen to be equal to the chip rate (12.7 MHz) and the sampling rate is correspondingly set at 50.8 Msamples/sec which is the Nyquist rate for the 25.4 MHz bandwidth IF signal. Finite wordlength effects have been simulated using the VANDA environment (1) to optimize the architecture and thereby minimize the chip area. The simulation results demonstrate that an IF input wordlength (A/D resolution) of 6 bits is more than sufficient to achieve a 10{dollar}sp{lcub}-5{rcub}{dollar} bit error rate (BER) at a {dollar}-17{dollar} dB IF signal-to-noise ratio (SNR) assuming an additive white Gaussian noise channel. The probability of PN acquisition and tracking within 5 msec is approximately 56 % at {dollar}-17{dollar} dB IF input SNR, 82 % at {dollar}-11{dollar} dB, and 100 % at 0 dB IF input SNR under an additive white Gaussian noise channel. The simulation results for simple two-ray multipath signals show that even without an adaptive equalizer the proposed IF receiver architecture can operate in a multipath environment except for the worst case of a quarter-chip multipath delay.