Experiments and simulation of plasma deposition and sputter etching processes

Planarization and step coverage of interlayer dielectric are the key issues in the successful fabrication of multilevel interconnection for advanced IC applications. A sequence of alternating steps of plasma enhanced CVD (PECVD) and sputter etch of dielectric is an important technique of attaining local planarization. In this work, phenomenological models for the PECVD, sputter etch, and biased electron cyclotron resonance (ECR) processes have been developed using the overhang test structure and a deposition and etching profile simulator. PECVD TEOS oxide deposition experiments on overhang structure of different heights and openings has been performed. The PECVD kinetic process is found to be explained by a linear combination of the CVD of a neutral precursor which has a constant reactive sticking coefficient, and an ion-induced growth component whose angular distribution is determined by the Kundsen number for the plasma sheath and the ratio of the charge exchange and momentum exchange cross sections. A methodology for the determination of geometric-invariant modeling parameters has been developed and lead to the successful simulation of experimental PECVD results for a variety of device geometries including the overhang structures and trenches of different aspect ratios.;A kinetic model for the argon sputter etch of SiO;Biased ECR SiH;A generalized plasma deposition and sputter etching model has been developed. The model has been implemented in SPEEDIE and leads to the development of a practical engineering tool which is capable of successfully simulating the deposition and sputter etch profiles encountered in interlayer dielectric fabrication.