Decision feedback detection for the digital magnetic storage channel

The continuing proliferation of computers throughout society and the demand for on-line access to information necessitate vast, inexpensive, and reliable data storage. Magnetic hard disk drive manufacturers strive to meet these needs by increasing storage density. The use of digital signal processing in the read channel, most notably the Partial-Response Maximum-Likelihood (PRML) detector, has contributed significant storage density gains. Coupled with an error correcting code (ECC), the detector recovers user data at error rates below {dollar}10sp{lcub}-14{rcub}{dollar}.; This dissertation focuses on the application of decision feedback detectors as a means for improving storage density. Decision feedback detectors recursively employ received data in the recovery of additional data. This results in two impairments--error propagation and a maximum throughput limit. We begin by characterizing the design and performance of a 54 Mbps RAM-Decision Feedback Equalizer (RAM-DFE) read channel. We show the RAM-DFE providing a bit error rate advantage over a PRML detector of similar complexity. However, experimental evidence also indicates that the RAM-DFE error statistics follow a bursty distribution due to error propagation. This defeats the ECC and results in unacceptable user error rates. We analyze the error propagation process and develop expressions for the error burst statistics that closely predict experimental results.; The impact of error propagation suggests that the detector bit error rate is not a meaningful performance metric. Rather, we analyze decision feedback detectors in terms of the sector error rate--the probability of at least one bit error in a sector of bits, after application of the ECC. We develop expressions that predict the loss in recording density due to error propagation. We also present new detector optimization criteria that constrain the feedback signal, thereby mitigating the effects of error propagation. The result is a small increase in the frequency of burst errors but a large decrease in the frequency of ECC-uncorrectable burst errors. The feedback constraints enable recording densities approaching error-free-feedback bounds. Alternatively, the feedback constraints provide several orders-of-magnitude in sector error rate margin.; Returning to the RAM-DFE read channel, we show decision feedback imposes a bottleneck on high throughput implementation. We propose eliminating the first feedback tap for moderate density applications. This results in a doubling of throughput without significant sector error rate degradation. We investigate a hybrid of linear and nonlinear feedback architectures that achieves 3 times the throughput of the RAM-DFE circuit with less than half the area. Finally, we develop a complete read channel chip based on the hybrid feedback architecture and demonstrate a throughput of 170 Mbps.