Design, fabrication, and characterization of shallow trench isolation and raised source/drains for 100nm CMOS

Device and process strategies for fully-scaled sub-100nm CMOS technologies are examined through simulation, fabrication and characterization. Channel termination by shallow trench isolation (STI) results in fringing gate fields that cause edge effects such as reduced threshold voltage. The impact of this edge effect on sub-250nm CMOS is explored through 3D device simulation, including impact of device and isolation design parameters and methods for minimizing the edge effect. Edge effects in conventional oxide-filled STI can be reduced using a gate step or rounded channel corner. A polysilicon field-plate in the STI reduces width-dependent threshold voltage roll-off by up to 85%. Oxide-filled and novel polysilicon-filled STI processes were developed for 50-100nm channel widths and 200-300nm isolation widths. NMOSFETs and test structures were fabricated, including splits for characterization of process options. Processes developed include Cl{dollar}sb2{dollar}-based trench RIE using O{dollar}sb2{dollar} and N{dollar}sb2{dollar} for profile control, LPCVD SiO{dollar}sb2{dollar} for void-free trench-filling, and CMP for planarization of oxide and polysilicon STI. Lateral oxidation during re-oxidation of polysilicon field-plate strongly affects channel width scalability. Fabricated MOSFETs show excellent electrical characteristics to 50nm channel widths. V{dollar}rmsb{lcub}TH{rcub}{dollar} roll-off at 100nm-channel width is 100% higher in oxide-filled STI compared to polysilicon-filled STI. A novel reversal of V{dollar}rmsb{lcub}TH{rcub}{dollar} roll-off was measured for the polysilicon-filed STI, and is attributed to implant screen oxide thickness variation. Sub-100nm channel widths exhibit less than 50mV V{dollar}rmsb{lcub}TH{rcub}{dollar} roll-off. V{dollar}rmsb{lcub}TH{rcub}{dollar} roll-off is sensitive to details of the trench corner as well as channel design parameters. Polysilicon-filled STI is attractive for the 100nm CMOS generation and beyond.; A W/SiGe/Si raised source/drain technology is proposed to address shallow junction and series resistance requirements. The SiGe overlayer serves as out-diffusion source and low series-resistance raised source-drain. Device simulation was used to evaluate integration of the W/SiGe/Si structure, including experimentally measured dopant profiles, SiGe sheet resistance, and W/SiGe contact resistivity. The W/SiGe/Si structure meets the series resistance needs of 100nm CMOS, but structures with contact resistivity greater than {dollar}1times10sp{lcub}-7{rcub}Omega{dollar}-cm{dollar}sp2{dollar} do not. Outdiffusion of dopants from implanted {dollar}rm Sisb{lcub}0.7{rcub}Gesb{lcub}0.3{rcub}{dollar} was demonstrated experimentally. Junction depths of 29-52nm were achieved for N+/P and P+/N junctions, with high surface concentrations, and excellent diode characteristics. Experimental and simulation results suggest that W/SiGe/Si is a viable raised source/drain technology through the 100nm CMOS generation, providing significant benefits in terms of process simplification and series resistance reduction.