Low-power and high-speed algorithms and VLSI architectures for error control coding and adaptive video scaling

Fueled by the advances in VLSI technology, signal processing systems are now coming into widespread use. A common feature of these systems are the challenging design requirements. The objective may be to increase speed, reduce power consumption, minimize area, reduce latency or a combination of these factors. We consider the application of algorithm/architecture level transformations to meet VLSI design requirements in video communication systems. We consider three challenging problems with varying requirements—Reed-Solomon (RS) decoding, turbo-MAP (Maximum Aposteriori Probability) decoding and adaptive video scaling.; RS codes are used widely for error correction in communication systems. We consider the problem of developing a low-power RS decoder. We propose transformations to the Berlekamp algorithm using the multirate technique that leads to a low-power/high speed VLSI implementation. A VLSI design was developed to show that a 40% reduction in power or a speed-up of 1.34 can be obtained.; Turbo codes are parallel concatenated convolutional codes that have a performance close to the Shannon limit. Turbo decoding commonly uses the SOVA (Soft Output Viterbi Algorithm) or the MAP algorithm. When turbo-decoding is used in small block transmission systems, the computational latency can be a critical factor in the overall latency of decoding. We propose an algorithm that reduces the computational latency in log-MAP implementations. We also investigate the relative complexities of the SOVA, log-MAP and the proposed low-latency log-MAP.; One approach to video transmission over a bandwidth limited channel is to send a compressed spatially scaled-down version of the video. High performance up-scaling of the video at the receiving end requires the use of adaptive scaling techniques that were considered too complex. We propose an efficient VLSI architecture that meets the challenging throughput requirements in real time adaptive scaling. The target was to scale QCIF video to CIF/4CIF video at 30 frames/s. We showed that a single chip implementation of such a system was feasible by estimating the silicon area.; In general, we showed that irrespective of the specific algorithm, transformations that use the underlying properties of the algorithm are effective in helping meet the system design requirements.