Jitter and phase noise in electrical oscillators

Providing a low phase noise local oscillator suitable for today's wireless world has been a major challenge in the field of mobile communication. Clock jitter of on-chip oscillators in modern microprocessors becomes a greater concern with each new, faster generation. As a result, there is a need for a deeper understanding of the fundamental mechanisms governing the process by which the device, substrate, and supply noise turn into jitter and phase noise.; To answer this demand, a new time-variant phase noise model is developed. Using this model, quantitative predictions are made for phase noise and jitter of various types of oscillators. Because of its time-variant nature, the model takes into account the effect of cyclostationary noise sources in a natural way. It explains the mechanism for upconversion of low frequency noise sources, such as 1/f noise, and the effect of the rise and fall time symmetry on its upconversion. The amplitude fluctuations are modeled in a similar fashion using the amplitude impulse response of the oscillator. The model reduces to previously available phase noise models as special cases. The theory is verified experimentally for a large number of oscillators with different topologies.; Closed-form expressions for the phase noise and jitter of ring oscillators in terms of power dissipation, frequency and other circuit parameters are obtained. The effect of substrate and supply noise on jitter and phase noise of ring oscillators is analyzed.; The phase noise of differential LC oscillators is also investigated. The effect of different noise sources in such oscillators is analyzed and methods for exploiting the cyclostationary properties of noise are shown. New design implications arising from this approach and experimental results are given.