| The need to overlay patterns in semiconductor circuit manufacturing to better than 20nm is now well recognized as a difficult and important challenge. Two broad strategies for meeting this challenge are described in this dissertation, one is physics-based and the other algorithm-based.; A physics-based approach is used to minimize the alignment errors resulting from asymmetric resist coating, the most ubiquitous cause of alignment errors. The technique employs transmagnetically polarized light at the Brewster angle of the resist. Experimental results show that resist-induced alignment errors as large as 25nm can be mitigated to less than 6nm by using this method.; We provide a general framework for designing advanced algorithms that are capable of correct alignment on marks that are damaged or distorted by various processing. One example, a subspace decomposition based algorithm, is applied to many types of mark damage and distortion. Experimental results show that for both artificially damaged marks and CMP-corrupted marks from a manufacturing process for which conventional algorithms failed (overlay errors of 200nm), the new method achieved a mean plus three sigma alignment error less than 50nm.; It is demonstrated that the combination of the physics- and algorithm-based techniques will be able to satisfy the overlay requirement of, and possibly beyond, the 0.13um generation of lithography. |
