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Novel high-k gate dielectric engineering and thermal stability of critical interfaces

Posted on:2000-05-05Degree:Ph.DType:Dissertation
University:The University of Texas at AustinCandidate:Mao, Yu-LungFull Text:PDF
GTID:1468390014961094Subject:Engineering
Abstract/Summary:
The interfacial stability of a gate stack structure, namely, metal gate/high K dielectrics/Si substrate, during the conventional rapid thermal CVD process and post-deposition annealing is an important key issue for advanced gate dielectric technology. Several surface analysis tools were utilized to perform such a task. Among them, X-ray Photoelectron Spectroscopy (XPS) was extensively used to study the film composition, chemical stoichiometry, and the layer structures throughout the work described in this dissertation.; The gate materials studied in this work include PVD platinum and CVD ruthenium and iridium. CVD Ta2O5 films were made and studied as promising candidate high K gate dielectrics. NH3-based Si3N4 and NO-based SiOxNy passivation layers were grown on Si(100) substrates to resist further oxidation and to inhibit reaction between high K dielectrics and the Si substrates. The annealing ambients involved in this work were NO, N2O, O2, N 2, Ar, and vacuum. Most of the film deposition and annealing processes, along with the film analysis, were implemented in an integrated CVD-surface analysis system equipped with a reaction chamber and in-situ XPS capability. Layer structures of certain films were examined by ex-situ Time-of-Flight Secondary Ion Mass Spectrometry (TOFSIMS) and ex-situ ARXPS in separate surface analysis system. Device characteristics and reliability of these films were evaluated by electrical measurement through standard MOS capacitor process.; The goal of this study was to keep the stack structurally and chemically stable during the entire thermal processing steps needed for device fabrication, while pursuing the thinnest equivalent oxide thickness (Tox, eq), superior film and interface properties, and enhanced reliability. There exists a material dependent annealing temperature above which certain stacked layers undergo significant thermal reactions. The thermodynamics, kinetics, and the material's inherent properties within the material were considered. Several evolution models were proposed to help understand certain instability processes.; This dissertation is aimed to provide a systematic study on the correlation between the electrical data and the chemical analysis involving the film deposition and the effects of post-deposition annealing, in oxidizing and non-oxidizing ambient, and post-metalization annealing, in non-oxidizing ambient, on the films and the associated interfaces, hoping to apply the principles to gate stack engineering for the future ULSI devices.
Keywords/Search Tags:Gate, Thermal, Stack, CVD, Film
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