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Multicast buffered ATM switch

Posted on:2000-02-04Degree:Ph.DType:Dissertation
University:North Carolina State UniversityCandidate:Vu, Chien DinhFull Text:PDF
GTID:1468390014466629Subject:Engineering
Abstract/Summary:
In this dissertation, we discuss ISDN and ATM architectures and ATM switching technology. We then study multicast switching technology through previously proposed and/or implemented multicast switches. We discuss in detail the three main functions of a multicast switch: buffering, replication, and switching, and focus primarily on the replication and switching mechanisms. We then propose a simple but robust switch architecture with new attractive features such as implicit routing tags and single table lookup. We investigate the performance of the proposal through modeling and simulation. The performance is compared with the performance of two recent ATM switches. The results show that the MBAS has the best performance while the Yamanaka is the worst. Under uniform traffic conditions with C2 = 1000, the MBAS latency is approximately 58% of the Abacus latency when system throughput is at 13.5%. When the system throughput reaches 74.5%, this ratio is 78%. Under nonuniform traffic conditions at the same burstiness, the ratios become 58% and 89% approximately. The results verify the superiority of the proposal over those switches and demonstrate that simplicity can be exploited for performance gain in switch architecture as it is in Reduced Instruction Set Computer architecture.
Keywords/Search Tags:ATM, Switch, Multicast, Architecture, Performance
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