| Network routers based on optoelectronic technology have the potential to solve the network bandwidth problem which is becoming more and more critical in multiprocessor systems. By combining high-bandwidth optoelectronic I/O technology and high-performance CMOS logic technology, optoelectronic network routers promise both sophisticated switching functions as well as ample bandwidth that scales well with the performance of current and next-generation processors. Performance analysis and implementation of optoelectronic routers or other optoelectronic chips with this level of complexity, however, have not been pursued to a great extent before. This dissertation uses analytical and semi-empirical models to quantify and estimate the performance of optoelectronic routers at the chip and system levels, and it studies the feasibility of implementing such routers using GaAs MESFET/LED/OPFET and CMOS/SEED integrated technologies. The results show that optoelectronic routers may not only be technologically viable but also can provide certain architectural advantages in multiprocessor systems. Nevertheless, as shown in this dissertation, three major requirements must be met to effectively utilize this new technology. First, small and robust packaging at the chip and system levels that ensure high-bandwidth operation at useful interconnection distances and topologies are needed. Second, optoelectronic compatible CAD tools that effectively integrate a large array of optoelectronic devices with complex circuitry while retaining the potential performance of optoelectronic chips are needed. Third, optoelectronic devices must have uniform characteristics and reliability. In addition, advanced architectural techniques that efficiently exploit high-bandwidth optical interconnects are also required. |
