Low-power architectures for video-object coding with low bit-rate applications

An algorithm-based low power VLSI architecture for video-object motion-tracking is presented. Power consumption is reduced at both algorithmic and arithmetic levels. The video-object is modeled as a 2D hierarchical structured mesh, the deformation of which represents the dynamics of the object across the video sequence. The algorithm benefits from the small number of bits that describe the mesh topology. Low power consumption is achieved at the algorithmic level: (1) by modeling the mesh as independent triangular patches that can be processed in parallel, (2) by hierarchically triangulating each patch using a structured technique, which can be pipelined using a simple unit, and (3) by using the three step search algorithm to simplify the motion estimation of the mesh nodes. At the arithmetic level, low power consumption is achieved by using an affine transformation that is multiplication-free.; VLSI architectures are developed based on the proposed algorithms. The main architectures are: a mesh-based motion estimation architecture and a mesh-based motion compensation architecture. The first architecture is based on a parallel block matching motion estimation to optimize the latency. The second architecture uses parallel threads. Each thread implements a pipelined chain of scalable multiplication-free affine units. The architectures have been prototyped and their performance measures have been evaluated. They can be used in online object-based video applications such as in MPEG-4, and VRML.