High-speed and low-power architectures for a hybrid video coder

The Block-Based model for motion estimation and compensation forms the basis of almost all video standards, for example MPEG-1, MPEG-2 and H.26x. Recently, the Mesh-Based model has been introduced in current video and graphics standards like MPEG-4 and VRML. It offers many functionalities that the Block-Based model does not offer. Therefore, a hybrid codec with Block-Based and Mesh-Based modes, which complement each other nicely, yields the best results over a wide range of video at low bit-rates. The work in this dissertation addresses the additions and enhancements to current Block-Based video coders to be able to incorporate the Mesh-Based model. Novel architectures for the key modules in the coder are proposed. A high-throughput VLSI architecture for the 2D Discrete Cosine Transform (DCT) that delivers 108 Gbps is proposed. It runs at 1.5 Ghz and consumes 0.45 Watts. Also, a survey of low-power architectures for Block-Based motion estimation is presented. A novel low-power architecture for Block-Based motion estimation is suggested based on this survey. It uses a hybrid tree/array structure. And finally, an architecture that performs motion compensation for both Block-Based and Mesh-Based models is presented. The main building block for these architectures is the binary adder. A detailed analysis of the 1-bit full-adder cell (the nucleus of the binary adder) is also presented in this dissertation. Comparison and simulation results of a wide variety of full-adders is performed. The best performing cell is used to build the VLSI architecture of the 2D-DCT.