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Dependable computing techniques for reconfigurable hardware

Posted on:2002-07-07Degree:Ph.DType:Dissertation
University:Stanford UniversityCandidate:Huang, Wei-JeFull Text:PDF
GTID:1468390011999078Subject:Engineering
Abstract/Summary:
Reconfigurable hardware, such as Field-Programmable Gate Arrays (FPGAs), has become a very important component in various applications, including communication networking, and storage systems. With the re-programmable feature and a tremendous increase in on-chip logic and routing resources, contemporary reconfigurable hardware also opens new opportunities in designing dependable systems with fine-grained hardware redundancy.; In traditional dependable systems using hardware redundancy, fault tolerance is realized by replicating functional modules at the level of a chip or a board. Such coarse-grained hardware redundancy is very expensive. In reconfigurable hardware, however, a more cost-effective method is made possible by using an alternative configuration in which the faulty parts are replaced with originally unused resources in the same device.; Dependable computing using reconfigurable hardware requires three layers of support. First, Concurrent Error Detection (CED) is required in order to guarantee the correctness of outputs and detect errors. Second, transient error recovery is needed to restore normal operations from failures due to temporary environmental disturbances. Third, permanent fault recovery, including fault location techniques and reconfiguration strategies for tolerating permanent faults, is required to repair a system with physical failures in the hardware. Since these techniques are executed at run-time, it is desired to minimize their performance impact and to ensure high availability.; We investigate the issues in each layer of support for dependable computing in reconfigurable hardware. For CED techniques, we present the inverse comparison scheme suitable for applications with unique inverses. For transient error recovery, we examine a memory coherence issue in the recovery process and present a dirty-bit memory coherence technique with low execution time overhead. For permanent fault recovery, we present an integrated scheme using the column-based precompiled configuration technique for repair and the blind reconfiguration approach for fault location. Our techniques ensure very fast and cost-effective fault recovery in reconfigurable, hardware...
Keywords/Search Tags:Hardware, Reconfigurable, Techniques, Dependable computing, Fault recovery
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