| This dissertation describes the Cache Filter Model, an analytical framework for cache system analysis. This framework provides a language and formal notation that enables researchers to reason and communicate about systems in an insightful new way. There are four major components that form the framework. First, the TSpec notation is a formal way for researchers to communicate with clarity about memory references generated by a processor. Second, the concept of an equivalence class to chance address bindings or specific inputs. Third, the functional cache filter model uses the TSpec notation and equivalence class concept to allow designers to more clearly understand the effects of cache systems on particular memory references. Fourth, new metrics provide more insight into cache system behavior than current measures such as hit rate or average memory access time. This dissertation presents the cache filter framework in detail and demonstrates its use on several example kernels. |
