| FinFET has begun to replace MOSFET at the 22nm technology node and beyond. Compared to planar CMOS, FinFET has higher on-current and lower leakage due to its double-gate structure. For system architects who wish to explore the use of this new technology, a FinFET-based simulation framework can be very helpful at the early design stages. However, such a simulator did not exist. Our work seeks to fill this gap. We present the details of one such simulation framework, called gem5-PVT, that we have developed. gem5-PVT leverages existing lower-level FinFET simulators to support timing, power, and thermal studies of FinFET-based chip multiprocessor (CMP) systems under process, voltage, and temperature (PVT) variations. It uses a bottom-up modeling approach based on logic/memory cell libraries that have been very accurately characterized using TCAD device simulation. This allows accuracy to bubble up to the system level. (Abstract shortened by ProQuest.). |
