Interface studies of high dielectric constant gate stack material

To extend the minimum feature size beyond the 100 nm node in Ultra-Large Scale Integration, a suitable replacement must be found for silicon dioxide in the gate region of field effect transistors (FET). To reduce the power consumption, the silicon dioxide thickness is typically reduced to decrease the threshold voltage (V_T) of the FET. The current thickness of silicon dioxide in production is about 2 nm, but any further reduction in thickness would increase the operating current exponentially due to quantum mechanical tunneling. The solution is to replace the silicon dioxide with a dielectric that has a significantly larger dielectric constant. This would allow a thicker gate dielectric to reduce current and threshold voltage at the same time, since V_T is inversely proportional to dielectric constant. Several possible replacements have been identified that form a thermodynamically stable interface with silicon dioxide, the most promising of which are zirconium dioxide (ZrO₂) and hafnium dioxide (HfO₂). However, the dynamics of the interfacial layer formed with silicon are not very well understood. This dissertation describes the study of the interface using electron diffraction tools, including identification of ultra-clean silicon preparation, deposition of hafnium dioxide using reactive electron beam evaporation, and the subsequent electrical characterization. Also included are the design and implementation of an ultra-high vacuum deposition system with in situ observation of the surface using electron diffraction and the electrical characterization of HfO₂ deposited in this chamber, as well as the characterization of subsequent films deposited in ultra-high vacuum.