| Portable, wireless, personal-communication devices continue to gain in popularity, and CMOS technology is becoming increasingly popular for the realization of key radio frequency components [6–8]. Although the intrinsic speed of scaled MOS devices is impressive, the use of CMOS devices for high-frequency applications has been limited by the “digital” orientation of the design and modelling environment. In particular, the optimum scaling, biasing, and tuning of the devices for the realization of the best high-frequency performance in a wireless environmental remains a challenge [9].; The purpose of this work is to develop some straightforward guidelines for simultaneously optimizing the linearity, noise, and dynamic range of the monolithic common-source MOS amplifier in an RF LNA, variable gain amplifier (VGA), and mixer applications in a wireless transceiver, under the constraint of minimizing do power dissipation. In a sense, this extends the earlier work of Schaefer and Lee [6] on power-constrained MOS LNA design to include linearity considerations. The experimental results presented verify the utility of this technique, and point the way towards fully monolithic CMOS transceivers with improved power/noise/linearity tradeoffs.; Following a brief introduction to RF systems and radio architecture, a detailed analysis of the device modelling, both active and passive, followed by prediction in performance from theory is made. Next, the theory of high-frequency linearity is developed to include nonlinear device behavior, impedance termination matching at the fundamental, second, and third harmonic, and feedback, followed by predictions. Next, noise modelling of MOS devices with feedback is developed and then the noise performance of the common-source amplifier is predicted. Next, an analysis of power-constrained dynamic range limitations on the MOS common-source amplifier and its implications on system performance requirements is discussed, concluding with predictions on tradeoffs.; Next, the theoretical techniques developed above are applied to the design of a 5 GHz low-power, high-linearity low-noise amplifier in a digital 0.35μm CMOS process. The circuit is simulated, fabricated, and tested.; A discussion detailing the test engineering necessary to verify all of the above results is provided. After which results from each area, device modelling, linearity, noise theory, RF optimization techniques, and circuit design are reviewed and compared to theoretical predictions. |
