METRICS: Automatic data collection infrastructure for continuous IC design process improvement

With increasing design complexity and shorter time-to-market windows, it is essential for designers to have tools and environments that can help them to design more effectively and efficiently. To achieve this improvement, one needs to measure and analyze the current design process. However, today there are no standards or infrastructure for measuring and recording the semiconductor design process. As a result, today's design processes tend to be temporary solutions, unique to individual projects and created based on the intuition of senior engineers. Such solutions typically last for one project only, while the basic problem of unpredictable design success remains unaddressed. Two fundamental gaps that prevent measurement of the design process are (i) data to be measured is not available, and (ii) we do not know all the data that should be measured.; Our work addresses the fundamental issues of understanding, diagnosing, optimizing, and predicting the IC design process. First, we present a new infrastructure that allows automatic data collection from the design process and provides various reporting capabilities to ease data analyses and integration of different diagnosis tools. A list of standard metrics, with standardized naming, is also proposed to enable consistent data collection across different tools in the flow. Second, we analyze various metrics of design quality, including measures of design complexity. A new complexity metric based on neighborhood structure, and several timing complexity metrics, are proposed along with their applications to a priori design estimation. Third, we outline a taxonomy of input noise and analyze the quality of EDA tools in the presence of that input noise. In addition, the strength of tools' incremental optimization capability is analyzed. Finally, we present several real applications as the proof of the concept. The applications are divided into three areas: (i) solution estimation, (ii) tool parameter generation, and (iii) sweet spot analysis. In the solution estimation area, the METRICS system is used in a clock planning methodology to suggest the clock frequency and the clock structure that is suitable for the design. In the tool parameter generation area, the METRICS system is used to search the best parameter for a given tool in order to minimize unnecessary iteration due to wrong parameter values. Last, in the sweet spot analysis area, the METRICS is used as front-end acceptance process that identifies incompatible design input, for the sweet spot analyzer area.